include/asm/iommu_32.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* iommu.h: Definitions for the sun4m IOMMU.
0003  *
0004  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
0005  */
0006 #ifndef _SPARC_IOMMU_H
0007 #define _SPARC_IOMMU_H
0008
0009 #include <asm/page.h>
0010 #include <asm/bitext.h>
0011
0012 /* The iommu handles all virtual to physical address translations
0013  * that occur between the SBUS and physical memory.  Access by
0014  * the cpu to IO registers and similar go over the mbus so are
0015  * translated by the on chip SRMMU.  The iommu and the srmmu do
0016  * not need to have the same translations at all, in fact most
0017  * of the time the translations they handle are a disjunct set.
0018  * Basically the iommu handles all dvma sbus activity.
0019  */
0020
0021 /* The IOMMU registers occupy three pages in IO space. */
0022 struct iommu_regs {
0023     /* First page */
0024     volatile unsigned long control;    /* IOMMU control */
0025     volatile unsigned long base;       /* Physical base of iopte page table */
0026     volatile unsigned long _unused1[3];
0027     volatile unsigned long tlbflush;   /* write only */
0028     volatile unsigned long pageflush;  /* write only */
0029     volatile unsigned long _unused2[1017];
0030     /* Second page */
0031     volatile unsigned long afsr;       /* Async-fault status register */
0032     volatile unsigned long afar;       /* Async-fault physical address */
0033     volatile unsigned long _unused3[2];
0034     volatile unsigned long sbuscfg0;   /* SBUS configuration registers, per-slot */
0035     volatile unsigned long sbuscfg1;
0036     volatile unsigned long sbuscfg2;
0037     volatile unsigned long sbuscfg3;
0038     volatile unsigned long mfsr;       /* Memory-fault status register */
0039     volatile unsigned long mfar;       /* Memory-fault physical address */
0040     volatile unsigned long _unused4[1014];
0041     /* Third page */
0042     volatile unsigned long mid;        /* IOMMU module-id */
0043 };
0044
0045 #define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
0046 #define IOMMU_CTRL_VERS     0x0f000000 /* Version */
0047 #define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
0048 #define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
0049 #define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
0050 #define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
0051 #define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
0052 #define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
0053 #define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
0054 #define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
0055 #define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
0056 #define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
0057
0058 #define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
0059 #define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after transaction */
0060 #define IOMMU_AFSR_TO       0x20000000 /* Write access took more than 12.8 us. */
0061 #define IOMMU_AFSR_BE       0x10000000 /* Write access received error acknowledge */
0062 #define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
0063 #define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
0064 #define IOMMU_AFSR_RESV     0x00f00000 /* Reserver, forced to 0x8 by hardware */
0065 #define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
0066 #define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
0067 #define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
0068
0069 #define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when bypass enabled */
0070 #define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
0071 #define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
0072 #define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
0073                       produced by this device as pure
0074                       physical. */
0075
0076 #define IOMMU_MFSR_ERR      0x80000000 /* One or more of PERR1 or PERR0 */
0077 #define IOMMU_MFSR_S        0x01000000 /* Sparc was in supervisor mode */
0078 #define IOMMU_MFSR_CPU      0x00800000 /* CPU transaction caused parity error */
0079 #define IOMMU_MFSR_ME       0x00080000 /* Multiple parity errors occurred */
0080 #define IOMMU_MFSR_PERR     0x00006000 /* high bit indicates parity error occurred
0081                       on the even word of the access, low bit
0082                       indicated odd word caused the parity error */
0083 #define IOMMU_MFSR_BM       0x00001000 /* Error occurred while in boot mode */
0084 #define IOMMU_MFSR_C        0x00000800 /* Address causing error was marked cacheable */
0085 #define IOMMU_MFSR_RTYP     0x000000f0 /* Memory request transaction type */
0086
0087 #define IOMMU_MID_SBAE      0x001f0000 /* SBus arbitration enable */
0088 #define IOMMU_MID_SE        0x00100000 /* Enables SCSI/ETHERNET arbitration */
0089 #define IOMMU_MID_SB3       0x00080000 /* Enable SBUS device 3 arbitration */
0090 #define IOMMU_MID_SB2       0x00040000 /* Enable SBUS device 2 arbitration */
0091 #define IOMMU_MID_SB1       0x00020000 /* Enable SBUS device 1 arbitration */
0092 #define IOMMU_MID_SB0       0x00010000 /* Enable SBUS device 0 arbitration */
0093 #define IOMMU_MID_MID       0x0000000f /* Module-id, hardcoded to 0x8 */
0094
0095 /* The format of an iopte in the page tables */
0096 #define IOPTE_PAGE          0x07ffff00 /* Physical page number (PA[30:12]) */
0097 #define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
0098 #define IOPTE_WRITE         0x00000004 /* Writeable */
0099 #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
0100 #define IOPTE_WAZ           0x00000001 /* Write as zeros */
0101
0102 struct iommu_struct {
0103     struct iommu_regs __iomem *regs;
0104     iopte_t *page_table;
0105     /* For convenience */
0106     unsigned long start; /* First managed virtual address */
0107     unsigned long end;   /* Last managed virtual address */
0108
0109     struct bit_map usemap;
0110 };
0111
0112 static inline void iommu_invalidate(struct iommu_regs __iomem *regs)
0113 {
0114     sbus_writel(0, &regs->tlbflush);
0115 }
0116
0117 static inline void iommu_invalidate_page(struct iommu_regs __iomem *regs, unsigned long ba)
0118 {
0119     sbus_writel(ba & PAGE_MASK, &regs->pageflush);
0120 }
0121
0122 #endif /* !(_SPARC_IOMMU_H) */