include/asm/estate.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _SPARC64_ESTATE_H
0003 #define _SPARC64_ESTATE_H
0004
0005 /* UltraSPARC-III E-cache Error Enable */
0006 #define ESTATE_ERROR_FMT    0x0000000000040000 /* Force MTAG ECC        */
0007 #define ESTATE_ERROR_FMESS  0x000000000003c000 /* Forced MTAG ECC val   */
0008 #define ESTATE_ERROR_FMD    0x0000000000002000 /* Force DATA ECC        */
0009 #define ESTATE_ERROR_FDECC  0x0000000000001ff0 /* Forced DATA ECC val   */
0010 #define ESTATE_ERROR_UCEEN  0x0000000000000008 /* See below         */
0011 #define ESTATE_ERROR_NCEEN  0x0000000000000002 /* See below         */
0012 #define ESTATE_ERROR_CEEN   0x0000000000000001 /* See below         */
0013
0014 /* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache
0015  * errors 2) uncorrectable E-cache errors.  Such events only occur on reads
0016  * of the E-cache by the local processor for: 1) data loads 2) instruction
0017  * fetches 3) atomic operations.  Such events _cannot_ occur for: 1) merge
0018  * 2) writeback 2) copyout.  The AFSR bits associated with these traps are
0019  * UCC and UCU.
0020  */
0021
0022 /* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps
0023  * for uncorrectable ECC errors and system errors.
0024  *
0025  * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT,
0026  * or system bus BusERR:
0027  * 1) As the result of an instruction fetch, will generate instruction_access_error
0028  * 2) As the result of a load etc. will generate data_access_error.
0029  * 3) As the result of store merge completion, writeback, or copyout will
0030  *    generate a disrupting ECC_error trap.
0031  * 4) As the result of such errors on instruction vector fetch can generate any
0032  *    of the 3 trap types.
0033  *
0034  * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE,
0035  * BERR, and TO.
0036  */
0037
0038 /* CEEN enables the ECC_error trap for hardware corrected ECC errors.  System bus
0039  * reads resulting in a hardware corrected data or MTAG ECC error will generate an
0040  * ECC_error disrupting trap with this bit enabled.
0041  *
0042  * This same trap will also be generated when a hardware corrected ECC error results
0043  * during store merge, writeback, and copyout operations.
0044  */
0045
0046 /* In general, if the trap enable bits above are disabled the AFSR bits will still
0047  * log the events even though the trap will not be generated by the processor.
0048  */
0049
0050 #endif /* _SPARC64_ESTATE_H */