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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 /* 0003 * ecc.h: Definitions and defines for the external cache/memory 0004 * controller on the sun4m. 0005 * 0006 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 0007 */ 0008 0009 #ifndef _SPARC_ECC_H 0010 #define _SPARC_ECC_H 0011 0012 /* These registers are accessed through the SRMMU passthrough ASI 0x20 */ 0013 #define ECC_ENABLE 0x00000000 /* ECC enable register */ 0014 #define ECC_FSTATUS 0x00000008 /* ECC fault status register */ 0015 #define ECC_FADDR 0x00000010 /* ECC fault address register */ 0016 #define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */ 0017 #define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */ 0018 #define ECC_DMESG 0x00001000 /* Diagnostic message passing area */ 0019 0020 /* ECC MBus Arbiter Enable register: 0021 * 0022 * ---------------------------------------- 0023 * | |SBUS|MOD3|MOD2|MOD1|RSV| 0024 * ---------------------------------------- 0025 * 31 5 4 3 2 1 0 0026 * 0027 * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on 0028 * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on 0029 * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on 0030 * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on 0031 */ 0032 0033 #define ECC_MBAE_SBUS 0x00000010 0034 #define ECC_MBAE_MOD3 0x00000008 0035 #define ECC_MBAE_MOD2 0x00000004 0036 #define ECC_MBAE_MOD1 0x00000002 0037 0038 /* ECC Fault Control Register layout: 0039 * 0040 * ----------------------------- 0041 * | RESV | ECHECK | EINT | 0042 * ----------------------------- 0043 * 31 2 1 0 0044 * 0045 * ECHECK: Enable ECC checking. 0=off 1=on 0046 * EINT: Enable Interrupts for correctable errors. 0=off 1=on 0047 */ 0048 #define ECC_FCR_CHECK 0x00000002 0049 #define ECC_FCR_INTENAB 0x00000001 0050 0051 /* ECC Fault Address Register Zero layout: 0052 * 0053 * ----------------------------------------------------- 0054 * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR | 0055 * ----------------------------------------------------- 0056 * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0 0057 * 0058 * MID: ModuleID of the faulting processor. ie. who did it? 0059 * S: Supervisor/Privileged access? 0=no 1=yes 0060 * VA: Bits 19-12 of the virtual faulting address, these are the 0061 * superset bits in the virtual cache and can be used for 0062 * a flush operation if necessary. 0063 * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot 0064 * mode bit. 0065 * AT: Did this fault happen during an atomic instruction? 0=no 0066 * 1=yes. This means either an 'ldstub' or 'swap' instruction 0067 * was in progress (but not finished) when this fault happened. 0068 * This indicated whether the bus was locked when the fault 0069 * occurred. 0070 * C: Did the pte for this access indicate that it was cacheable? 0071 * 0=no 1=yes 0072 * SZ: The size of the transaction. 0073 * TYP: The transaction type. 0074 * PADDR: Bits 35-32 of the physical address for the fault. 0075 */ 0076 #define ECC_FADDR0_MIDMASK 0xf0000000 0077 #define ECC_FADDR0_S 0x08000000 0078 #define ECC_FADDR0_VADDR 0x003fc000 0079 #define ECC_FADDR0_BMODE 0x00002000 0080 #define ECC_FADDR0_ATOMIC 0x00001000 0081 #define ECC_FADDR0_CACHE 0x00000800 0082 #define ECC_FADDR0_SIZE 0x00000700 0083 #define ECC_FADDR0_TYPE 0x000000f0 0084 #define ECC_FADDR0_PADDR 0x0000000f 0085 0086 /* ECC Fault Address Register One layout: 0087 * 0088 * ------------------------------------- 0089 * | Physical Address 31-0 | 0090 * ------------------------------------- 0091 * 31 0 0092 * 0093 * You get the upper 4 bits of the physical address from the 0094 * PADDR field in ECC Fault Address Zero register. 0095 */ 0096 0097 /* ECC Fault Status Register layout: 0098 * 0099 * ---------------------------------------------- 0100 * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C| 0101 * ---------------------------------------------- 0102 * 31-18 17 16 15-8 7-4 3 2 1 0 0103 * 0104 * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only) 0105 * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes) 0106 * SYNDROME: Controller is mentally unstable. 0107 * DWORD: 0108 * UNC: Uncorrectable error. 0=no 1=yes 0109 * TIMEO: Timeout occurred. 0=no 1=yes 0110 * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only) 0111 * C: Correctable error? 0=no 1=yes 0112 */ 0113 0114 #define ECC_FSR_C2ERR 0x00020000 0115 #define ECC_FSR_MULT 0x00010000 0116 #define ECC_FSR_SYND 0x0000ff00 0117 #define ECC_FSR_DWORD 0x000000f0 0118 #define ECC_FSR_UNC 0x00000008 0119 #define ECC_FSR_TIMEO 0x00000004 0120 #define ECC_FSR_BADSLOT 0x00000002 0121 #define ECC_FSR_C 0x00000001 0122 0123 #endif /* !(_SPARC_ECC_H) */
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