include/asm/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_SPARC_DMA_H
0003 #define _ASM_SPARC_DMA_H
0004
0005 /* These are irrelevant for Sparc DMA, but we leave it in so that
0006  * things can compile.
0007  */
0008 #define MAX_DMA_CHANNELS 8
0009 #define DMA_MODE_READ    1
0010 #define DMA_MODE_WRITE   2
0011 #define MAX_DMA_ADDRESS  (~0UL)
0012
0013 /* Useful constants */
0014 #define SIZE_16MB      (16*1024*1024)
0015 #define SIZE_64K       (64*1024)
0016
0017 /* SBUS DMA controller reg offsets */
0018 #define DMA_CSR     0x00UL      /* rw  DMA control/status register    0x00   */
0019 #define DMA_ADDR    0x04UL      /* rw  DMA transfer address register  0x04   */
0020 #define DMA_COUNT   0x08UL      /* rw  DMA transfer count register    0x08   */
0021 #define DMA_TEST    0x0cUL      /* rw  DMA test/debug register        0x0c   */
0022
0023 /* Fields in the cond_reg register */
0024 /* First, the version identification bits */
0025 #define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
0026 #define DMA_VERS0        0x00000000        /* Sunray DMA version */
0027 #define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
0028 #define DMA_VERS1        0x80000000        /* DMA rev 1 */
0029 #define DMA_VERS2        0xa0000000        /* DMA rev 2 */
0030 #define DMA_VERHME       0xb0000000        /* DMA hme gate array */
0031 #define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
0032
0033 #define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
0034 #define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
0035 #define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
0036 #define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
0037 #define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
0038 #define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
0039 #define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
0040 #define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
0041 #define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
0042 #define DMA_ST_WRITE     0x00000100        /* write from device to memory */
0043 #define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
0044 #define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
0045 #define DMA_ESC_BURST    0x00000800        /* 1=16byte 0=32byte */
0046 #define DMA_READ_AHEAD   0x00001800        /* DMA read ahead partial longword */
0047 #define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
0048 #define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
0049 #define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
0050 #define DMA_SCSI_SBUS64  0x00008000        /* HME: Enable 64-bit SBUS mode. */
0051 #define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
0052 #define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
0053 #define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
0054 #define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
0055 #define DMA_E_BURSTS     0x000c0000    /* ENET: SBUS r/w burst mask */
0056 #define DMA_E_BURST32    0x00040000    /* ENET: SBUS 32 byte r/w burst */
0057 #define DMA_E_BURST16    0x00000000    /* ENET: SBUS 16 byte r/w burst */
0058 #define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
0059 #define DMA_BRST64       0x000c0000        /* SCSI: 64byte bursts (HME on UltraSparc only) */
0060 #define DMA_BRST32       0x00040000        /* SCSI: 32byte bursts */
0061 #define DMA_BRST16       0x00000000        /* SCSI: 16byte bursts */
0062 #define DMA_BRST0        0x00080000        /* SCSI: no bursts (non-HME gate arrays) */
0063 #define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
0064 #define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
0065 #define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
0066 #define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
0067 #define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
0068 #define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
0069 #define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
0070 #define DMA_PARITY_OFF   0x02000000        /* HME: disable parity checking */
0071 #define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
0072 #define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
0073 #define DMA_RESET_FAS366 0x08000000        /* HME: Assert RESET to FAS366 */
0074
0075 /* Values describing the burst-size property from the PROM */
0076 #define DMA_BURST1       0x01
0077 #define DMA_BURST2       0x02
0078 #define DMA_BURST4       0x04
0079 #define DMA_BURST8       0x08
0080 #define DMA_BURST16      0x10
0081 #define DMA_BURST32      0x20
0082 #define DMA_BURST64      0x40
0083 #define DMA_BURSTBITS    0x7f
0084
0085 #ifdef CONFIG_SPARC32
0086 struct device;
0087
0088 unsigned long sparc_dma_alloc_resource(struct device *dev, size_t len);
0089 bool sparc_dma_free_resource(void *cpu_addr, size_t size);
0090 #endif
0091
0092 #endif /* !(_ASM_SPARC_DMA_H) */