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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 #ifndef _SPARC64_CHAFSR_H 0003 #define _SPARC64_CHAFSR_H 0004 0005 /* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */ 0006 0007 /* Comments indicate which processor variants on which the bit definition 0008 * is valid. Codes are: 0009 * ch --> cheetah 0010 * ch+ --> cheetah plus 0011 * jp --> jalapeno 0012 */ 0013 0014 /* All bits of this register except M_SYNDROME and E_SYNDROME are 0015 * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only. 0016 */ 0017 0018 /* Software bit set by linux trap handlers to indicate that the trap was 0019 * signalled at %tl >= 1. 0020 */ 0021 #define CHAFSR_TL1 (1UL << 63UL) /* n/a */ 0022 0023 /* Unmapped error from system bus for prefetch queue or 0024 * store queue read operation 0025 */ 0026 #define CHPAFSR_DTO (1UL << 59UL) /* ch+ */ 0027 0028 /* Bus error from system bus for prefetch queue or store queue 0029 * read operation 0030 */ 0031 #define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */ 0032 0033 /* Hardware corrected E-cache Tag ECC error */ 0034 #define CHPAFSR_THCE (1UL << 57UL) /* ch+ */ 0035 /* System interface protocol error, hw timeout caused */ 0036 #define JPAFSR_JETO (1UL << 57UL) /* jp */ 0037 0038 /* SW handled correctable E-cache Tag ECC error */ 0039 #define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */ 0040 /* Parity error on system snoop results */ 0041 #define JPAFSR_SCE (1UL << 56UL) /* jp */ 0042 0043 /* Uncorrectable E-cache Tag ECC error */ 0044 #define CHPAFSR_TUE (1UL << 55UL) /* ch+ */ 0045 /* System interface protocol error, illegal command detected */ 0046 #define JPAFSR_JEIC (1UL << 55UL) /* jp */ 0047 0048 /* Uncorrectable system bus data ECC error due to prefetch 0049 * or store fill request 0050 */ 0051 #define CHPAFSR_DUE (1UL << 54UL) /* ch+ */ 0052 /* System interface protocol error, illegal ADTYPE detected */ 0053 #define JPAFSR_JEIT (1UL << 54UL) /* jp */ 0054 0055 /* Multiple errors of the same type have occurred. This bit is set when 0056 * an uncorrectable error or a SW correctable error occurs and the status 0057 * bit to report that error is already set. When multiple errors of 0058 * different types are indicated by setting multiple status bits. 0059 * 0060 * This bit is not set if multiple HW corrected errors with the same 0061 * status bit occur, only uncorrectable and SW correctable ones have 0062 * this behavior. 0063 * 0064 * This bit is not set when multiple ECC errors happen within a single 0065 * 64-byte system bus transaction. Only the first ECC error in a 16-byte 0066 * subunit will be logged. All errors in subsequent 16-byte subunits 0067 * from the same 64-byte transaction are ignored. 0068 */ 0069 #define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */ 0070 0071 /* Privileged state error has occurred. This is a capture of PSTATE.PRIV 0072 * at the time the error is detected. 0073 */ 0074 #define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */ 0075 0076 /* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error 0077 * bits and record the most recently detected errors. Bits accumulate 0078 * errors that have been detected since the last write to clear the bit. 0079 */ 0080 0081 /* System interface protocol error. The processor asserts its' ERROR 0082 * pin when this event occurs and it also logs a specific cause code 0083 * into a JTAG scannable flop. 0084 */ 0085 #define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */ 0086 0087 /* Internal processor error. The processor asserts its' ERROR 0088 * pin when this event occurs and it also logs a specific cause code 0089 * into a JTAG scannable flop. 0090 */ 0091 #define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */ 0092 0093 /* System request parity error on incoming address */ 0094 #define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */ 0095 0096 /* HW Corrected system bus MTAG ECC error */ 0097 #define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */ 0098 /* Parity error on L2 cache tag SRAM */ 0099 #define JPAFSR_ETP (1UL << 48UL) /* jp */ 0100 0101 /* Uncorrectable system bus MTAG ECC error */ 0102 #define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */ 0103 /* Out of range memory error has occurred */ 0104 #define JPAFSR_OM (1UL << 47UL) /* jp */ 0105 0106 /* HW Corrected system bus data ECC error for read of interrupt vector */ 0107 #define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */ 0108 /* Error due to unsupported store */ 0109 #define JPAFSR_UMS (1UL << 46UL) /* jp */ 0110 0111 /* Uncorrectable system bus data ECC error for read of interrupt vector */ 0112 #define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */ 0113 0114 /* Unmapped error from system bus */ 0115 #define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */ 0116 0117 /* Bus error response from system bus */ 0118 #define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */ 0119 0120 /* SW Correctable E-cache ECC error for instruction fetch or data access 0121 * other than block load. 0122 */ 0123 #define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */ 0124 0125 /* Uncorrectable E-cache ECC error for instruction fetch or data access 0126 * other than block load. 0127 */ 0128 #define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */ 0129 0130 /* Copyout HW Corrected ECC error */ 0131 #define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */ 0132 0133 /* Copyout Uncorrectable ECC error */ 0134 #define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */ 0135 0136 /* HW Corrected ECC error from E-cache for writeback */ 0137 #define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */ 0138 0139 /* Uncorrectable ECC error from E-cache for writeback */ 0140 #define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */ 0141 0142 /* HW Corrected ECC error from E-cache for store merge or block load */ 0143 #define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */ 0144 0145 /* Uncorrectable ECC error from E-cache for store merge or block load */ 0146 #define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */ 0147 0148 /* Uncorrectable system bus data ECC error for read of memory or I/O */ 0149 #define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */ 0150 0151 /* HW Corrected system bus data ECC error for read of memory or I/O */ 0152 #define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */ 0153 0154 /* Uncorrectable ECC error from remote cache/memory */ 0155 #define JPAFSR_RUE (1UL << 32UL) /* jp */ 0156 0157 /* Correctable ECC error from remote cache/memory */ 0158 #define JPAFSR_RCE (1UL << 31UL) /* jp */ 0159 0160 /* JBUS parity error on returned read data */ 0161 #define JPAFSR_BP (1UL << 30UL) /* jp */ 0162 0163 /* JBUS parity error on data for writeback or block store */ 0164 #define JPAFSR_WBP (1UL << 29UL) /* jp */ 0165 0166 /* Foreign read to DRAM incurring correctable ECC error */ 0167 #define JPAFSR_FRC (1UL << 28UL) /* jp */ 0168 0169 /* Foreign read to DRAM incurring uncorrectable ECC error */ 0170 #define JPAFSR_FRU (1UL << 27UL) /* jp */ 0171 0172 #define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ 0173 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ 0174 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ 0175 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ 0176 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) 0177 #define CHPAFSR_ERRORS (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \ 0178 CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \ 0179 CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ 0180 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ 0181 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ 0182 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ 0183 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) 0184 #define JPAFSR_ERRORS (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \ 0185 JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \ 0186 CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \ 0187 JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \ 0188 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \ 0189 CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \ 0190 CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \ 0191 CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \ 0192 JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \ 0193 JPAFSR_FRC | JPAFSR_FRU) 0194 0195 /* Active JBUS request signal when error occurred */ 0196 #define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */ 0197 #define JPAFSR_JBREQ_SHIFT 24UL 0198 0199 /* L2 cache way information */ 0200 #define JPAFSR_ETW (0x3UL << 22UL) /* jp */ 0201 #define JPAFSR_ETW_SHIFT 22UL 0202 0203 /* System bus MTAG ECC syndrome. This field captures the status of the 0204 * first occurrence of the highest-priority error according to the M_SYND 0205 * overwrite policy. After the AFSR sticky bit, corresponding to the error 0206 * for which the M_SYND is reported, is cleared, the contents of the M_SYND 0207 * field will be unchanged by will be unfrozen for further error capture. 0208 */ 0209 #define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */ 0210 #define CHAFSR_M_SYNDROME_SHIFT 16UL 0211 0212 /* Agenid Id of the foreign device causing the UE/CE errors */ 0213 #define JPAFSR_AID (0x1fUL << 9UL) /* jp */ 0214 #define JPAFSR_AID_SHIFT 9UL 0215 0216 /* System bus or E-cache data ECC syndrome. This field captures the status 0217 * of the first occurrence of the highest-priority error according to the 0218 * E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the 0219 * error for which the E_SYND is reported, is cleare, the contents of the E_SYND 0220 * field will be unchanged but will be unfrozen for further error capture. 0221 */ 0222 #define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */ 0223 #define CHAFSR_E_SYNDROME_SHIFT 0UL 0224 0225 /* The AFSR must be explicitly cleared by software, it is not cleared automatically 0226 * by a read. Writes to bits <51:33> with bits set will clear the corresponding 0227 * bits in the AFSR. Bits associated with disrupting traps must be cleared before 0228 * interrupts are re-enabled to prevent multiple traps for the same error. I.e. 0229 * PSTATE.IE and AFSR bits control delivery of disrupting traps. 0230 * 0231 * Since there is only one AFAR, when multiple events have been logged by the 0232 * bits in the AFSR, at most one of these events will have its status captured 0233 * in the AFAR. The highest priority of those event bits will get AFAR logging. 0234 * The AFAR will be unlocked and available to capture the address of another event 0235 * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is 0236 * cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites 0237 * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked 0238 * and ready for another event, even though AFSR.CE is still set. The same rules 0239 * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR. 0240 */ 0241 0242 #endif /* _SPARC64_CHAFSR_H */
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