Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Perf PMU sysfs events attributes for available CPU-measurement counters
0004  *
0005  */
0006 
0007 #include <linux/slab.h>
0008 #include <linux/perf_event.h>
0009 #include <asm/cpu_mf.h>
0010 
0011 
0012 /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
0013 
0014 CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
0015 CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
0016 CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
0017 CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
0018 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
0019 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
0020 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
0021 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
0022 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
0023 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
0024 CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004);
0025 CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005);
0026 CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000);
0027 CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001);
0028 CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002);
0029 CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003);
0030 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020);
0031 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
0032 CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
0033 CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
0034 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_FUNCTIONS, 0x0040);
0035 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_CYCLES, 0x0041);
0036 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS, 0x0042);
0037 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_CYCLES, 0x0043);
0038 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_FUNCTIONS, 0x0044);
0039 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_CYCLES, 0x0045);
0040 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS, 0x0046);
0041 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_CYCLES, 0x0047);
0042 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_FUNCTIONS, 0x0048);
0043 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_CYCLES, 0x0049);
0044 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS, 0x004a);
0045 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_CYCLES, 0x004b);
0046 CPUMF_EVENT_ATTR(cf_svn_12345, AES_FUNCTIONS, 0x004c);
0047 CPUMF_EVENT_ATTR(cf_svn_12345, AES_CYCLES, 0x004d);
0048 CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS, 0x004e);
0049 CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_CYCLES, 0x004f);
0050 CPUMF_EVENT_ATTR(cf_svn_6, ECC_FUNCTION_COUNT, 0x0050);
0051 CPUMF_EVENT_ATTR(cf_svn_6, ECC_CYCLES_COUNT, 0x0051);
0052 CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT, 0x0052);
0053 CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT, 0x0053);
0054 CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
0055 CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
0056 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
0057 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
0058 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
0059 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
0060 CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
0061 CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
0062 CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
0063 CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
0064 CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
0065 CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
0066 CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
0067 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
0068 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
0069 CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
0070 CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
0071 CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
0072 CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
0073 CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
0074 CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
0075 CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
0076 CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
0077 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
0078 CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
0079 CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
0080 CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
0081 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
0082 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
0083 CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
0084 CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
0085 CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
0086 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
0087 CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
0088 CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
0089 CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
0090 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
0091 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
0092 CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
0093 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
0094 CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
0095 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
0096 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
0097 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
0098 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
0099 CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
0100 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
0101 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
0102 CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
0103 CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
0104 CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
0105 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
0106 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
0107 CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
0108 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
0109 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
0110 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
0111 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
0112 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
0113 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
0114 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
0115 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
0116 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
0117 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
0118 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
0119 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
0120 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
0121 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
0122 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
0123 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
0124 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
0125 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
0126 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
0127 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
0128 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
0129 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
0130 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
0131 CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080);
0132 CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081);
0133 CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082);
0134 CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083);
0135 CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084);
0136 CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085);
0137 CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086);
0138 CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087);
0139 CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088);
0140 CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089);
0141 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a);
0142 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b);
0143 CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c);
0144 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d);
0145 CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f);
0146 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
0147 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091);
0148 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092);
0149 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093);
0150 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094);
0151 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095);
0152 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096);
0153 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097);
0154 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098);
0155 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099);
0156 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a);
0157 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b);
0158 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c);
0159 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d);
0160 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e);
0161 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f);
0162 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0);
0163 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1);
0164 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
0165 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3);
0166 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4);
0167 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5);
0168 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6);
0169 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7);
0170 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8);
0171 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9);
0172 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa);
0173 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab);
0174 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac);
0175 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad);
0176 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae);
0177 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af);
0178 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0);
0179 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1);
0180 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2);
0181 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3);
0182 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da);
0183 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
0184 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
0185 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
0186 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
0187 CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080);
0188 CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081);
0189 CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082);
0190 CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083);
0191 CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084);
0192 CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085);
0193 CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086);
0194 CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087);
0195 CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088);
0196 CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089);
0197 CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a);
0198 CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b);
0199 CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c);
0200 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d);
0201 CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f);
0202 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
0203 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
0204 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
0205 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
0206 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
0207 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
0208 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
0209 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
0210 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
0211 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
0212 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
0213 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
0214 CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
0215 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
0216 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
0217 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
0218 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
0219 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
0220 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
0221 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
0222 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
0223 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
0224 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
0225 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
0226 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
0227 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
0228 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
0229 CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
0230 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
0231 CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
0232 CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1);
0233 CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2);
0234 CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8);
0235 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3);
0236 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
0237 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
0238 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
0239 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
0240 
0241 CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
0242 CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
0243 CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
0244 CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
0245 CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
0246 CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
0247 CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
0248 CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
0249 CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
0250 CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
0251 CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
0252 CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
0253 CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
0254 CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
0255 CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
0256 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
0257 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
0258 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
0259 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
0260 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
0261 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
0262 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
0263 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
0264 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
0265 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
0266 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
0267 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
0268 CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
0269 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
0270 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
0271 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
0272 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
0273 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
0274 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
0275 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
0276 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
0277 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
0278 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
0279 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
0280 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
0281 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
0282 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
0283 CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
0284 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
0285 CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
0286 CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
0287 CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
0288 CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
0289 CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
0290 CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
0291 CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
0292 CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
0293 CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
0294 CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
0295 CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109);
0296 CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
0297 CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
0298 CPUMF_EVENT_ATTR(cf_z16, L1D_RO_EXCL_WRITES, 0x0080);
0299 CPUMF_EVENT_ATTR(cf_z16, DTLB2_WRITES, 0x0081);
0300 CPUMF_EVENT_ATTR(cf_z16, DTLB2_MISSES, 0x0082);
0301 CPUMF_EVENT_ATTR(cf_z16, CRSTE_1MB_WRITES, 0x0083);
0302 CPUMF_EVENT_ATTR(cf_z16, DTLB2_GPAGE_WRITES, 0x0084);
0303 CPUMF_EVENT_ATTR(cf_z16, ITLB2_WRITES, 0x0086);
0304 CPUMF_EVENT_ATTR(cf_z16, ITLB2_MISSES, 0x0087);
0305 CPUMF_EVENT_ATTR(cf_z16, TLB2_PTE_WRITES, 0x0089);
0306 CPUMF_EVENT_ATTR(cf_z16, TLB2_CRSTE_WRITES, 0x008a);
0307 CPUMF_EVENT_ATTR(cf_z16, TLB2_ENGINES_BUSY, 0x008b);
0308 CPUMF_EVENT_ATTR(cf_z16, TX_C_TEND, 0x008c);
0309 CPUMF_EVENT_ATTR(cf_z16, TX_NC_TEND, 0x008d);
0310 CPUMF_EVENT_ATTR(cf_z16, L1C_TLB2_MISSES, 0x008f);
0311 CPUMF_EVENT_ATTR(cf_z16, DCW_REQ, 0x0091);
0312 CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_IV, 0x0092);
0313 CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_CHIP_HIT, 0x0093);
0314 CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_DRAWER_HIT, 0x0094);
0315 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP, 0x0095);
0316 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_IV, 0x0096);
0317 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_CHIP_HIT, 0x0097);
0318 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT, 0x0098);
0319 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE, 0x0099);
0320 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER, 0x009a);
0321 CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER, 0x009b);
0322 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_MEMORY, 0x009c);
0323 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE_MEMORY, 0x009d);
0324 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER_MEMORY, 0x009e);
0325 CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER_MEMORY, 0x009f);
0326 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_IV, 0x00a0);
0327 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT, 0x00a1);
0328 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2);
0329 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_IV, 0x00a3);
0330 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4);
0331 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5);
0332 CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_IV, 0x00a6);
0333 CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7);
0334 CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8);
0335 CPUMF_EVENT_ATTR(cf_z16, ICW_REQ, 0x00a9);
0336 CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_IV, 0x00aa);
0337 CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_CHIP_HIT, 0x00ab);
0338 CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_DRAWER_HIT, 0x00ac);
0339 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP, 0x00ad);
0340 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_IV, 0x00ae);
0341 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_CHIP_HIT, 0x00af);
0342 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT, 0x00b0);
0343 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE, 0x00b1);
0344 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER, 0x00b2);
0345 CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER, 0x00b3);
0346 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_MEMORY, 0x00b4);
0347 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE_MEMORY, 0x00b5);
0348 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER_MEMORY, 0x00b6);
0349 CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER_MEMORY, 0x00b7);
0350 CPUMF_EVENT_ATTR(cf_z16, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
0351 CPUMF_EVENT_ATTR(cf_z16, VX_BCD_EXECUTION_SLOTS, 0x00e1);
0352 CPUMF_EVENT_ATTR(cf_z16, DECIMAL_INSTRUCTIONS, 0x00e2);
0353 CPUMF_EVENT_ATTR(cf_z16, LAST_HOST_TRANSLATIONS, 0x00e8);
0354 CPUMF_EVENT_ATTR(cf_z16, TX_NC_TABORT, 0x00f4);
0355 CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_NO_SPECIAL, 0x00f5);
0356 CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_SPECIAL, 0x00f6);
0357 CPUMF_EVENT_ATTR(cf_z16, DFLT_ACCESS, 0x00f8);
0358 CPUMF_EVENT_ATTR(cf_z16, DFLT_CYCLES, 0x00fd);
0359 CPUMF_EVENT_ATTR(cf_z16, SORTL, 0x0100);
0360 CPUMF_EVENT_ATTR(cf_z16, DFLT_CC, 0x0109);
0361 CPUMF_EVENT_ATTR(cf_z16, DFLT_CCFINISH, 0x010a);
0362 CPUMF_EVENT_ATTR(cf_z16, NNPA_INVOCATIONS, 0x010b);
0363 CPUMF_EVENT_ATTR(cf_z16, NNPA_COMPLETIONS, 0x010c);
0364 CPUMF_EVENT_ATTR(cf_z16, NNPA_WAIT_LOCK, 0x010d);
0365 CPUMF_EVENT_ATTR(cf_z16, NNPA_HOLD_LOCK, 0x010e);
0366 CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
0367 CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
0368 
0369 static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
0370     CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
0371     CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
0372     CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES),
0373     CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES),
0374     CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES),
0375     CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS),
0376     CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES),
0377     CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES),
0378     CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES),
0379     CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES),
0380     CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES),
0381     CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES),
0382     NULL,
0383 };
0384 
0385 static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = {
0386     CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES),
0387     CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS),
0388     CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES),
0389     CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES),
0390     CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES),
0391     CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS),
0392     CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES),
0393     CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES),
0394     NULL,
0395 };
0396 
0397 static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
0398     CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
0399     CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
0400     CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
0401     CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
0402     CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
0403     CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
0404     CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
0405     CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
0406     CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
0407     CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
0408     CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
0409     CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
0410     CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
0411     CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
0412     CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
0413     CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
0414     NULL,
0415 };
0416 
0417 static struct attribute *cpumcf_svn_67_pmu_event_attr[] __initdata = {
0418     CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
0419     CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
0420     CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
0421     CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
0422     CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
0423     CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
0424     CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
0425     CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
0426     CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
0427     CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
0428     CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
0429     CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
0430     CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
0431     CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
0432     CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
0433     CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
0434     CPUMF_EVENT_PTR(cf_svn_6, ECC_FUNCTION_COUNT),
0435     CPUMF_EVENT_PTR(cf_svn_6, ECC_CYCLES_COUNT),
0436     CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT),
0437     CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT),
0438     NULL,
0439 };
0440 
0441 static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
0442     CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
0443     CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
0444     CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
0445     CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
0446     CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
0447     CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
0448     CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
0449     CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
0450     CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
0451     CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
0452     CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
0453     CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
0454     CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
0455     CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
0456     CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
0457     CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
0458     CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
0459     CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
0460     NULL,
0461 };
0462 
0463 static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
0464     CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
0465     CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
0466     CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
0467     CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
0468     CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
0469     CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
0470     CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
0471     CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
0472     CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
0473     CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
0474     CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
0475     CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
0476     CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
0477     CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
0478     CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
0479     CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
0480     CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
0481     CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
0482     CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
0483     CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
0484     CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
0485     CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
0486     CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
0487     CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
0488     NULL,
0489 };
0490 
0491 static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
0492     CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
0493     CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
0494     CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
0495     CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
0496     CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
0497     CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
0498     CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
0499     CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
0500     CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
0501     CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
0502     CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
0503     CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
0504     CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
0505     CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
0506     CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
0507     CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
0508     CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
0509     CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
0510     CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
0511     CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
0512     CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
0513     CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
0514     CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
0515     CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
0516     CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
0517     CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
0518     CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
0519     CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
0520     CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
0521     CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
0522     CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
0523     CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
0524     CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
0525     CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
0526     CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
0527     NULL,
0528 };
0529 
0530 static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
0531     CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES),
0532     CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES),
0533     CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES),
0534     CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES),
0535     CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES),
0536     CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES),
0537     CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES),
0538     CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES),
0539     CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES),
0540     CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES),
0541     CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES),
0542     CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES),
0543     CPUMF_EVENT_PTR(cf_z13, TX_C_TEND),
0544     CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND),
0545     CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES),
0546     CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES),
0547     CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
0548     CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES),
0549     CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV),
0550     CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES),
0551     CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES),
0552     CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV),
0553     CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES),
0554     CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
0555     CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
0556     CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
0557     CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
0558     CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
0559     CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
0560     CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES),
0561     CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES),
0562     CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES),
0563     CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES),
0564     CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES),
0565     CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
0566     CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES),
0567     CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV),
0568     CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES),
0569     CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES),
0570     CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV),
0571     CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES),
0572     CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
0573     CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
0574     CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
0575     CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
0576     CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
0577     CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
0578     CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES),
0579     CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES),
0580     CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES),
0581     CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES),
0582     CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT),
0583     CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL),
0584     CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL),
0585     CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
0586     CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
0587     NULL,
0588 };
0589 
0590 static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
0591     CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES),
0592     CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES),
0593     CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES),
0594     CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES),
0595     CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES),
0596     CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES),
0597     CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES),
0598     CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES),
0599     CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES),
0600     CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES),
0601     CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES),
0602     CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY),
0603     CPUMF_EVENT_PTR(cf_z14, TX_C_TEND),
0604     CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND),
0605     CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES),
0606     CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES),
0607     CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
0608     CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
0609     CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES),
0610     CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
0611     CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
0612     CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
0613     CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
0614     CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
0615     CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES),
0616     CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
0617     CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
0618     CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES),
0619     CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES),
0620     CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
0621     CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES),
0622     CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
0623     CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
0624     CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES),
0625     CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
0626     CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
0627     CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
0628     CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
0629     CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
0630     CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES),
0631     CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
0632     CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
0633     CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES),
0634     CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES),
0635     CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS),
0636     CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS),
0637     CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS),
0638     CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS),
0639     CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT),
0640     CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL),
0641     CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL),
0642     CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
0643     CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
0644     NULL,
0645 };
0646 
0647 static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
0648     CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
0649     CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
0650     CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
0651     CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
0652     CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
0653     CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
0654     CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
0655     CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
0656     CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
0657     CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
0658     CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
0659     CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
0660     CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
0661     CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
0662     CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
0663     CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
0664     CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
0665     CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
0666     CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
0667     CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
0668     CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
0669     CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
0670     CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
0671     CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
0672     CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
0673     CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
0674     CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
0675     CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
0676     CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
0677     CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
0678     CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
0679     CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
0680     CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
0681     CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
0682     CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
0683     CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
0684     CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
0685     CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
0686     CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
0687     CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
0688     CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
0689     CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
0690     CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
0691     CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
0692     CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
0693     CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
0694     CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
0695     CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
0696     CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
0697     CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
0698     CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
0699     CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
0700     CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
0701     CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
0702     CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH),
0703     CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
0704     CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
0705     NULL,
0706 };
0707 
0708 static struct attribute *cpumcf_z16_pmu_event_attr[] __initdata = {
0709     CPUMF_EVENT_PTR(cf_z16, L1D_RO_EXCL_WRITES),
0710     CPUMF_EVENT_PTR(cf_z16, DTLB2_WRITES),
0711     CPUMF_EVENT_PTR(cf_z16, DTLB2_MISSES),
0712     CPUMF_EVENT_PTR(cf_z16, CRSTE_1MB_WRITES),
0713     CPUMF_EVENT_PTR(cf_z16, DTLB2_GPAGE_WRITES),
0714     CPUMF_EVENT_PTR(cf_z16, ITLB2_WRITES),
0715     CPUMF_EVENT_PTR(cf_z16, ITLB2_MISSES),
0716     CPUMF_EVENT_PTR(cf_z16, TLB2_PTE_WRITES),
0717     CPUMF_EVENT_PTR(cf_z16, TLB2_CRSTE_WRITES),
0718     CPUMF_EVENT_PTR(cf_z16, TLB2_ENGINES_BUSY),
0719     CPUMF_EVENT_PTR(cf_z16, TX_C_TEND),
0720     CPUMF_EVENT_PTR(cf_z16, TX_NC_TEND),
0721     CPUMF_EVENT_PTR(cf_z16, L1C_TLB2_MISSES),
0722     CPUMF_EVENT_PTR(cf_z16, DCW_REQ),
0723     CPUMF_EVENT_PTR(cf_z16, DCW_REQ_IV),
0724     CPUMF_EVENT_PTR(cf_z16, DCW_REQ_CHIP_HIT),
0725     CPUMF_EVENT_PTR(cf_z16, DCW_REQ_DRAWER_HIT),
0726     CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP),
0727     CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_IV),
0728     CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_CHIP_HIT),
0729     CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT),
0730     CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE),
0731     CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER),
0732     CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER),
0733     CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_MEMORY),
0734     CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE_MEMORY),
0735     CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER_MEMORY),
0736     CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER_MEMORY),
0737     CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_IV),
0738     CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT),
0739     CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT),
0740     CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_IV),
0741     CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT),
0742     CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT),
0743     CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_IV),
0744     CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT),
0745     CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT),
0746     CPUMF_EVENT_PTR(cf_z16, ICW_REQ),
0747     CPUMF_EVENT_PTR(cf_z16, ICW_REQ_IV),
0748     CPUMF_EVENT_PTR(cf_z16, ICW_REQ_CHIP_HIT),
0749     CPUMF_EVENT_PTR(cf_z16, ICW_REQ_DRAWER_HIT),
0750     CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP),
0751     CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_IV),
0752     CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_CHIP_HIT),
0753     CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT),
0754     CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE),
0755     CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER),
0756     CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER),
0757     CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_MEMORY),
0758     CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE_MEMORY),
0759     CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER_MEMORY),
0760     CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER_MEMORY),
0761     CPUMF_EVENT_PTR(cf_z16, BCD_DFP_EXECUTION_SLOTS),
0762     CPUMF_EVENT_PTR(cf_z16, VX_BCD_EXECUTION_SLOTS),
0763     CPUMF_EVENT_PTR(cf_z16, DECIMAL_INSTRUCTIONS),
0764     CPUMF_EVENT_PTR(cf_z16, LAST_HOST_TRANSLATIONS),
0765     CPUMF_EVENT_PTR(cf_z16, TX_NC_TABORT),
0766     CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_NO_SPECIAL),
0767     CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_SPECIAL),
0768     CPUMF_EVENT_PTR(cf_z16, DFLT_ACCESS),
0769     CPUMF_EVENT_PTR(cf_z16, DFLT_CYCLES),
0770     CPUMF_EVENT_PTR(cf_z16, SORTL),
0771     CPUMF_EVENT_PTR(cf_z16, DFLT_CC),
0772     CPUMF_EVENT_PTR(cf_z16, DFLT_CCFINISH),
0773     CPUMF_EVENT_PTR(cf_z16, NNPA_INVOCATIONS),
0774     CPUMF_EVENT_PTR(cf_z16, NNPA_COMPLETIONS),
0775     CPUMF_EVENT_PTR(cf_z16, NNPA_WAIT_LOCK),
0776     CPUMF_EVENT_PTR(cf_z16, NNPA_HOLD_LOCK),
0777     CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
0778     CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
0779     NULL,
0780 };
0781 
0782 /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
0783 
0784 static struct attribute_group cpumcf_pmu_events_group = {
0785     .name = "events",
0786 };
0787 
0788 PMU_FORMAT_ATTR(event, "config:0-63");
0789 
0790 static struct attribute *cpumcf_pmu_format_attr[] = {
0791     &format_attr_event.attr,
0792     NULL,
0793 };
0794 
0795 static struct attribute_group cpumcf_pmu_format_group = {
0796     .name = "format",
0797     .attrs = cpumcf_pmu_format_attr,
0798 };
0799 
0800 static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
0801     &cpumcf_pmu_events_group,
0802     &cpumcf_pmu_format_group,
0803     NULL,
0804 };
0805 
0806 
0807 static __init struct attribute **merge_attr(struct attribute **a,
0808                         struct attribute **b,
0809                         struct attribute **c)
0810 {
0811     struct attribute **new;
0812     int j, i;
0813 
0814     for (j = 0; a[j]; j++)
0815         ;
0816     for (i = 0; b[i]; i++)
0817         j++;
0818     for (i = 0; c[i]; i++)
0819         j++;
0820     j++;
0821 
0822     new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL);
0823     if (!new)
0824         return NULL;
0825     j = 0;
0826     for (i = 0; a[i]; i++)
0827         new[j++] = a[i];
0828     for (i = 0; b[i]; i++)
0829         new[j++] = b[i];
0830     for (i = 0; c[i]; i++)
0831         new[j++] = c[i];
0832     new[j] = NULL;
0833 
0834     return new;
0835 }
0836 
0837 __init const struct attribute_group **cpumf_cf_event_group(void)
0838 {
0839     struct attribute **combined, **model, **cfvn, **csvn;
0840     struct attribute *none[] = { NULL };
0841     struct cpumf_ctr_info ci;
0842     struct cpuid cpu_id;
0843 
0844     /* Determine generic counters set(s) */
0845     qctri(&ci);
0846     switch (ci.cfvn) {
0847     case 1:
0848         cfvn = cpumcf_fvn1_pmu_event_attr;
0849         break;
0850     case 3:
0851         cfvn = cpumcf_fvn3_pmu_event_attr;
0852         break;
0853     default:
0854         cfvn = none;
0855     }
0856 
0857     /* Determine version specific crypto set */
0858     switch (ci.csvn) {
0859     case 1 ... 5:
0860         csvn = cpumcf_svn_12345_pmu_event_attr;
0861         break;
0862     case 6 ... 7:
0863         csvn = cpumcf_svn_67_pmu_event_attr;
0864         break;
0865     default:
0866         csvn = none;
0867     }
0868 
0869     /* Determine model-specific counter set(s) */
0870     get_cpu_id(&cpu_id);
0871     switch (cpu_id.machine) {
0872     case 0x2097:
0873     case 0x2098:
0874         model = cpumcf_z10_pmu_event_attr;
0875         break;
0876     case 0x2817:
0877     case 0x2818:
0878         model = cpumcf_z196_pmu_event_attr;
0879         break;
0880     case 0x2827:
0881     case 0x2828:
0882         model = cpumcf_zec12_pmu_event_attr;
0883         break;
0884     case 0x2964:
0885     case 0x2965:
0886         model = cpumcf_z13_pmu_event_attr;
0887         break;
0888     case 0x3906:
0889     case 0x3907:
0890         model = cpumcf_z14_pmu_event_attr;
0891         break;
0892     case 0x8561:
0893     case 0x8562:
0894         model = cpumcf_z15_pmu_event_attr;
0895         break;
0896     case 0x3931:
0897     case 0x3932:
0898         model = cpumcf_z16_pmu_event_attr;
0899         break;
0900     default:
0901         model = none;
0902         break;
0903     }
0904 
0905     combined = merge_attr(cfvn, csvn, model);
0906     if (combined)
0907         cpumcf_pmu_events_group.attrs = combined;
0908     return cpumcf_pmu_attr_groups;
0909 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!