include/asm/tlb.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _S390_TLB_H
0003 #define _S390_TLB_H
0004
0005 /*
0006  * TLB flushing on s390 is complicated. The following requirement
0007  * from the principles of operation is the most arduous:
0008  *
0009  * "A valid table entry must not be changed while it is attached
0010  * to any CPU and may be used for translation by that CPU except to
0011  * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
0012  * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
0013  * table entry, or (3) make a change by means of a COMPARE AND SWAP
0014  * AND PURGE instruction that purges the TLB."
0015  *
0016  * The modification of a pte of an active mm struct therefore is
0017  * a two step process: i) invalidate the pte, ii) store the new pte.
0018  * This is true for the page protection bit as well.
0019  * The only possible optimization is to flush at the beginning of
0020  * a tlb_gather_mmu cycle if the mm_struct is currently not in use.
0021  *
0022  * Pages used for the page tables is a different story. FIXME: more
0023  */
0024
0025 void __tlb_remove_table(void *_table);
0026 static inline void tlb_flush(struct mmu_gather *tlb);
0027 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
0028                       struct page *page, int page_size);
0029
0030 #define tlb_flush tlb_flush
0031 #define pte_free_tlb pte_free_tlb
0032 #define pmd_free_tlb pmd_free_tlb
0033 #define p4d_free_tlb p4d_free_tlb
0034 #define pud_free_tlb pud_free_tlb
0035
0036 #include <asm/tlbflush.h>
0037 #include <asm-generic/tlb.h>
0038
0039 /*
0040  * Release the page cache reference for a pte removed by
0041  * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
0042  * has already been freed, so just do free_page_and_swap_cache.
0043  */
0044 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
0045                       struct page *page, int page_size)
0046 {
0047     free_page_and_swap_cache(page);
0048     return false;
0049 }
0050
0051 static inline void tlb_flush(struct mmu_gather *tlb)
0052 {
0053     __tlb_flush_mm_lazy(tlb->mm);
0054 }
0055
0056 /*
0057  * pte_free_tlb frees a pte table and clears the CRSTE for the
0058  * page table from the tlb.
0059  */
0060 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
0061                                 unsigned long address)
0062 {
0063     __tlb_adjust_range(tlb, address, PAGE_SIZE);
0064     tlb->mm->context.flush_mm = 1;
0065     tlb->freed_tables = 1;
0066     tlb->cleared_pmds = 1;
0067     /*
0068      * page_table_free_rcu takes care of the allocation bit masks
0069      * of the 2K table fragments in the 4K page table page,
0070      * then calls tlb_remove_table.
0071      */
0072     page_table_free_rcu(tlb, (unsigned long *) pte, address);
0073 }
0074
0075 /*
0076  * pmd_free_tlb frees a pmd table and clears the CRSTE for the
0077  * segment table entry from the tlb.
0078  * If the mm uses a two level page table the single pmd is freed
0079  * as the pgd. pmd_free_tlb checks the asce_limit against 2GB
0080  * to avoid the double free of the pmd in this case.
0081  */
0082 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
0083                 unsigned long address)
0084 {
0085     if (mm_pmd_folded(tlb->mm))
0086         return;
0087     pgtable_pmd_page_dtor(virt_to_page(pmd));
0088     __tlb_adjust_range(tlb, address, PAGE_SIZE);
0089     tlb->mm->context.flush_mm = 1;
0090     tlb->freed_tables = 1;
0091     tlb->cleared_puds = 1;
0092     tlb_remove_table(tlb, pmd);
0093 }
0094
0095 /*
0096  * p4d_free_tlb frees a pud table and clears the CRSTE for the
0097  * region second table entry from the tlb.
0098  * If the mm uses a four level page table the single p4d is freed
0099  * as the pgd. p4d_free_tlb checks the asce_limit against 8PB
0100  * to avoid the double free of the p4d in this case.
0101  */
0102 static inline void p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d,
0103                 unsigned long address)
0104 {
0105     if (mm_p4d_folded(tlb->mm))
0106         return;
0107     __tlb_adjust_range(tlb, address, PAGE_SIZE);
0108     tlb->mm->context.flush_mm = 1;
0109     tlb->freed_tables = 1;
0110     tlb_remove_table(tlb, p4d);
0111 }
0112
0113 /*
0114  * pud_free_tlb frees a pud table and clears the CRSTE for the
0115  * region third table entry from the tlb.
0116  * If the mm uses a three level page table the single pud is freed
0117  * as the pgd. pud_free_tlb checks the asce_limit against 4TB
0118  * to avoid the double free of the pud in this case.
0119  */
0120 static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
0121                 unsigned long address)
0122 {
0123     if (mm_pud_folded(tlb->mm))
0124         return;
0125     tlb->mm->context.flush_mm = 1;
0126     tlb->freed_tables = 1;
0127     tlb->cleared_p4ds = 1;
0128     tlb_remove_table(tlb, pud);
0129 }
0130
0131
0132 #endif /* _S390_TLB_H */