include/asm/processor.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  S390 version
0004  *    Copyright IBM Corp. 1999
0005  *    Author(s): Hartmut Penner (hp@de.ibm.com),
0006  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
0007  *
0008  *  Derived from "include/asm-i386/processor.h"
0009  *    Copyright (C) 1994, Linus Torvalds
0010  */
0011
0012 #ifndef __ASM_S390_PROCESSOR_H
0013 #define __ASM_S390_PROCESSOR_H
0014
0015 #include <linux/bits.h>
0016
0017 #define CIF_NOHZ_DELAY      2   /* delay HZ disable for a tick */
0018 #define CIF_FPU         3   /* restore FPU registers */
0019 #define CIF_ENABLED_WAIT    5   /* in enabled wait state */
0020 #define CIF_MCCK_GUEST      6   /* machine check happening in guest */
0021 #define CIF_DEDICATED_CPU   7   /* this CPU is dedicated */
0022
0023 #define _CIF_NOHZ_DELAY     BIT(CIF_NOHZ_DELAY)
0024 #define _CIF_FPU        BIT(CIF_FPU)
0025 #define _CIF_ENABLED_WAIT   BIT(CIF_ENABLED_WAIT)
0026 #define _CIF_MCCK_GUEST     BIT(CIF_MCCK_GUEST)
0027 #define _CIF_DEDICATED_CPU  BIT(CIF_DEDICATED_CPU)
0028
0029 #define RESTART_FLAG_CTLREGS    _AC(1 << 0, U)
0030
0031 #ifndef __ASSEMBLY__
0032
0033 #include <linux/cpumask.h>
0034 #include <linux/linkage.h>
0035 #include <linux/irqflags.h>
0036 #include <asm/cpu.h>
0037 #include <asm/page.h>
0038 #include <asm/ptrace.h>
0039 #include <asm/setup.h>
0040 #include <asm/runtime_instr.h>
0041 #include <asm/fpu/types.h>
0042 #include <asm/fpu/internal.h>
0043 #include <asm/irqflags.h>
0044
0045 typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
0046
0047 static inline void set_cpu_flag(int flag)
0048 {
0049     S390_lowcore.cpu_flags |= (1UL << flag);
0050 }
0051
0052 static inline void clear_cpu_flag(int flag)
0053 {
0054     S390_lowcore.cpu_flags &= ~(1UL << flag);
0055 }
0056
0057 static inline int test_cpu_flag(int flag)
0058 {
0059     return !!(S390_lowcore.cpu_flags & (1UL << flag));
0060 }
0061
0062 /*
0063  * Test CIF flag of another CPU. The caller needs to ensure that
0064  * CPU hotplug can not happen, e.g. by disabling preemption.
0065  */
0066 static inline int test_cpu_flag_of(int flag, int cpu)
0067 {
0068     struct lowcore *lc = lowcore_ptr[cpu];
0069     return !!(lc->cpu_flags & (1UL << flag));
0070 }
0071
0072 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
0073
0074 static inline void get_cpu_id(struct cpuid *ptr)
0075 {
0076     asm volatile("stidp %0" : "=Q" (*ptr));
0077 }
0078
0079 void s390_adjust_jiffies(void);
0080 void s390_update_cpu_mhz(void);
0081 void cpu_detect_mhz_feature(void);
0082
0083 extern const struct seq_operations cpuinfo_op;
0084 extern void execve_tail(void);
0085 extern void __bpon(void);
0086 unsigned long vdso_size(void);
0087
0088 /*
0089  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
0090  */
0091
0092 #define TASK_SIZE       (test_thread_flag(TIF_31BIT) ? \
0093                     _REGION3_SIZE : TASK_SIZE_MAX)
0094 #define TASK_UNMAPPED_BASE  (test_thread_flag(TIF_31BIT) ? \
0095                     (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
0096 #define TASK_SIZE_MAX       (-PAGE_SIZE)
0097
0098 #define VDSO_BASE       (STACK_TOP + PAGE_SIZE)
0099 #define VDSO_LIMIT      (test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
0100 #define STACK_TOP       (VDSO_LIMIT - vdso_size() - PAGE_SIZE)
0101 #define STACK_TOP_MAX       (_REGION2_SIZE - vdso_size() - PAGE_SIZE)
0102
0103 #define HAVE_ARCH_PICK_MMAP_LAYOUT
0104
0105 /*
0106  * Thread structure
0107  */
0108 struct thread_struct {
0109     unsigned int  acrs[NUM_ACRS];
0110     unsigned long ksp;          /* kernel stack pointer */
0111     unsigned long user_timer;       /* task cputime in user space */
0112     unsigned long guest_timer;      /* task cputime in kvm guest */
0113     unsigned long system_timer;     /* task cputime in kernel space */
0114     unsigned long hardirq_timer;        /* task cputime in hardirq context */
0115     unsigned long softirq_timer;        /* task cputime in softirq context */
0116     const sys_call_ptr_t *sys_call_table;   /* system call table address */
0117     unsigned long gmap_addr;        /* address of last gmap fault. */
0118     unsigned int gmap_write_flag;       /* gmap fault write indication */
0119     unsigned int gmap_int_code;     /* int code of last gmap fault */
0120     unsigned int gmap_pfault;       /* signal of a pending guest pfault */
0121
0122     /* Per-thread information related to debugging */
0123     struct per_regs per_user;       /* User specified PER registers */
0124     struct per_event per_event;     /* Cause of the last PER trap */
0125     unsigned long per_flags;        /* Flags to control debug behavior */
0126     unsigned int system_call;       /* system call number in signal */
0127     unsigned long last_break;       /* last breaking-event-address. */
0128     /* pfault_wait is used to block the process on a pfault event */
0129     unsigned long pfault_wait;
0130     struct list_head list;
0131     /* cpu runtime instrumentation */
0132     struct runtime_instr_cb *ri_cb;
0133     struct gs_cb *gs_cb;            /* Current guarded storage cb */
0134     struct gs_cb *gs_bc_cb;         /* Broadcast guarded storage cb */
0135     struct pgm_tdb trap_tdb;        /* Transaction abort diagnose block */
0136     /*
0137      * Warning: 'fpu' is dynamically-sized. It *MUST* be at
0138      * the end.
0139      */
0140     struct fpu fpu;         /* FP and VX register save area */
0141 };
0142
0143 /* Flag to disable transactions. */
0144 #define PER_FLAG_NO_TE          1UL
0145 /* Flag to enable random transaction aborts. */
0146 #define PER_FLAG_TE_ABORT_RAND      2UL
0147 /* Flag to specify random transaction abort mode:
0148  * - abort each transaction at a random instruction before TEND if set.
0149  * - abort random transactions at a random instruction if cleared.
0150  */
0151 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
0152
0153 typedef struct thread_struct thread_struct;
0154
0155 #define ARCH_MIN_TASKALIGN  8
0156
0157 #define INIT_THREAD {                           \
0158     .ksp = sizeof(init_stack) + (unsigned long) &init_stack,    \
0159     .fpu.regs = (void *) init_task.thread.fpu.fprs,         \
0160     .last_break = 1,                        \
0161 }
0162
0163 /*
0164  * Do necessary setup to start up a new thread.
0165  */
0166 #define start_thread(regs, new_psw, new_stackp) do {            \
0167     regs->psw.mask  = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;    \
0168     regs->psw.addr  = new_psw;                  \
0169     regs->gprs[15]  = new_stackp;                   \
0170     execve_tail();                          \
0171 } while (0)
0172
0173 #define start_thread31(regs, new_psw, new_stackp) do {          \
0174     regs->psw.mask  = PSW_USER_BITS | PSW_MASK_BA;          \
0175     regs->psw.addr  = new_psw;                  \
0176     regs->gprs[15]  = new_stackp;                   \
0177     execve_tail();                          \
0178 } while (0)
0179
0180 /* Forward declaration, a strange C thing */
0181 struct task_struct;
0182 struct mm_struct;
0183 struct seq_file;
0184 struct pt_regs;
0185
0186 void show_registers(struct pt_regs *regs);
0187 void show_cacheinfo(struct seq_file *m);
0188
0189 /* Free all resources held by a thread. */
0190 static inline void release_thread(struct task_struct *tsk) { }
0191
0192 /* Free guarded storage control block */
0193 void guarded_storage_release(struct task_struct *tsk);
0194 void gs_load_bc_cb(struct pt_regs *regs);
0195
0196 unsigned long __get_wchan(struct task_struct *p);
0197 #define task_pt_regs(tsk) ((struct pt_regs *) \
0198         (task_stack_page(tsk) + THREAD_SIZE) - 1)
0199 #define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
0200 #define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
0201
0202 /* Has task runtime instrumentation enabled ? */
0203 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
0204
0205 register unsigned long current_stack_pointer asm("r15");
0206
0207 static __always_inline unsigned short stap(void)
0208 {
0209     unsigned short cpu_address;
0210
0211     asm volatile("stap %0" : "=Q" (cpu_address));
0212     return cpu_address;
0213 }
0214
0215 #define cpu_relax() barrier()
0216
0217 #define ECAG_CACHE_ATTRIBUTE    0
0218 #define ECAG_CPU_ATTRIBUTE  1
0219
0220 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
0221 {
0222     unsigned long val;
0223
0224     asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
0225     return val;
0226 }
0227
0228 static inline void psw_set_key(unsigned int key)
0229 {
0230     asm volatile("spka 0(%0)" : : "d" (key));
0231 }
0232
0233 /*
0234  * Set PSW to specified value.
0235  */
0236 static inline void __load_psw(psw_t psw)
0237 {
0238     asm volatile("lpswe %0" : : "Q" (psw) : "cc");
0239 }
0240
0241 /*
0242  * Set PSW mask to specified value, while leaving the
0243  * PSW addr pointing to the next instruction.
0244  */
0245 static __always_inline void __load_psw_mask(unsigned long mask)
0246 {
0247     unsigned long addr;
0248     psw_t psw;
0249
0250     psw.mask = mask;
0251
0252     asm volatile(
0253         "   larl    %0,1f\n"
0254         "   stg %0,%1\n"
0255         "   lpswe   %2\n"
0256         "1:"
0257         : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
0258 }
0259
0260 /*
0261  * Extract current PSW mask
0262  */
0263 static inline unsigned long __extract_psw(void)
0264 {
0265     unsigned int reg1, reg2;
0266
0267     asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
0268     return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
0269 }
0270
0271 static inline void local_mcck_enable(void)
0272 {
0273     __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
0274 }
0275
0276 static inline void local_mcck_disable(void)
0277 {
0278     __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
0279 }
0280
0281 /*
0282  * Rewind PSW instruction address by specified number of bytes.
0283  */
0284 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
0285 {
0286     unsigned long mask;
0287
0288     mask = (psw.mask & PSW_MASK_EA) ? -1UL :
0289            (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
0290                       (1UL << 24) - 1;
0291     return (psw.addr - ilc) & mask;
0292 }
0293
0294 /*
0295  * Function to drop a processor into disabled wait state
0296  */
0297 static __always_inline void __noreturn disabled_wait(void)
0298 {
0299     psw_t psw;
0300
0301     psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
0302     psw.addr = _THIS_IP_;
0303     __load_psw(psw);
0304     while (1);
0305 }
0306
0307 #define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
0308
0309 extern int memcpy_real(void *, unsigned long, size_t);
0310 extern void memcpy_absolute(void *, void *, size_t);
0311
0312 #define put_abs_lowcore(member, x) do {                 \
0313     unsigned long __abs_address = offsetof(struct lowcore, member); \
0314     __typeof__(((struct lowcore *)0)->member) __tmp = (x);      \
0315                                     \
0316     memcpy_absolute(__va(__abs_address), &__tmp, sizeof(__tmp));    \
0317 } while (0)
0318
0319 #define get_abs_lowcore(x, member) do {                 \
0320     unsigned long __abs_address = offsetof(struct lowcore, member); \
0321     __typeof__(((struct lowcore *)0)->member) *__ptr = &(x);    \
0322                                     \
0323     memcpy_absolute(__ptr, __va(__abs_address), sizeof(*__ptr));    \
0324 } while (0)
0325
0326 extern int s390_isolate_bp(void);
0327 extern int s390_isolate_bp_guest(void);
0328
0329 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
0330 {
0331     return arch_irqs_disabled_flags(regs->psw.mask);
0332 }
0333
0334 #endif /* __ASSEMBLY__ */
0335
0336 #endif /* __ASM_S390_PROCESSOR_H */