include/asm/pci_clp.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_S390_PCI_CLP_H
0003 #define _ASM_S390_PCI_CLP_H
0004
0005 #include <asm/clp.h>
0006
0007 /*
0008  * Call Logical Processor - Command Codes
0009  */
0010 #define CLP_SLPC        0x0001
0011 #define CLP_LIST_PCI        0x0002
0012 #define CLP_QUERY_PCI_FN    0x0003
0013 #define CLP_QUERY_PCI_FNGRP 0x0004
0014 #define CLP_SET_PCI_FN      0x0005
0015
0016 /* PCI function handle list entry */
0017 struct clp_fh_list_entry {
0018     u16 device_id;
0019     u16 vendor_id;
0020     u32 config_state :  1;
0021     u32      : 31;
0022     u32 fid;        /* PCI function id */
0023     u32 fh;         /* PCI function handle */
0024 } __packed;
0025
0026 #define CLP_RC_SETPCIFN_FH  0x0101  /* Invalid PCI fn handle */
0027 #define CLP_RC_SETPCIFN_FHOP    0x0102  /* Fn handle not valid for op */
0028 #define CLP_RC_SETPCIFN_DMAAS   0x0103  /* Invalid DMA addr space */
0029 #define CLP_RC_SETPCIFN_RES 0x0104  /* Insufficient resources */
0030 #define CLP_RC_SETPCIFN_ALRDY   0x0105  /* Fn already in requested state */
0031 #define CLP_RC_SETPCIFN_ERR 0x0106  /* Fn in permanent error state */
0032 #define CLP_RC_SETPCIFN_RECPND  0x0107  /* Error recovery pending */
0033 #define CLP_RC_SETPCIFN_BUSY    0x0108  /* Fn busy */
0034 #define CLP_RC_LISTPCI_BADRT    0x010a  /* Resume token not recognized */
0035 #define CLP_RC_QUERYPCIFG_PFGID 0x010b  /* Unrecognized PFGID */
0036
0037 /* request or response block header length */
0038 #define LIST_PCI_HDR_LEN    32
0039
0040 /* Number of function handles fitting in response block */
0041 #define CLP_FH_LIST_NR_ENTRIES              \
0042     ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN)      \
0043         / sizeof(struct clp_fh_list_entry))
0044
0045 #define CLP_SET_ENABLE_PCI_FN   0   /* Yes, 0 enables it */
0046 #define CLP_SET_DISABLE_PCI_FN  1   /* Yes, 1 disables it */
0047 #define CLP_SET_ENABLE_MIO  2
0048 #define CLP_SET_DISABLE_MIO 3
0049
0050 #define CLP_UTIL_STR_LEN    64
0051 #define CLP_PFIP_NR_SEGMENTS    4
0052
0053 extern bool zpci_unique_uid;
0054
0055 struct clp_rsp_slpc_pci {
0056     struct clp_rsp_hdr hdr;
0057     u32 reserved2[4];
0058     u32 lpif[8];
0059     u32 reserved3[4];
0060     u32 vwb     :  1;
0061     u32     :  1;
0062     u32 mio_wb  :  6;
0063     u32     : 24;
0064     u32 reserved5[3];
0065     u32 lpic[8];
0066 } __packed;
0067
0068 /* List PCI functions request */
0069 struct clp_req_list_pci {
0070     struct clp_req_hdr hdr;
0071     u64 resume_token;
0072     u64 reserved2;
0073 } __packed;
0074
0075 /* List PCI functions response */
0076 struct clp_rsp_list_pci {
0077     struct clp_rsp_hdr hdr;
0078     u64 resume_token;
0079     u32 reserved2;
0080     u16 max_fn;
0081     u8          : 7;
0082     u8 uid_checking     : 1;
0083     u8 entry_size;
0084     struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
0085 } __packed;
0086
0087 struct mio_info {
0088     u32 valid : 6;
0089     u32 : 26;
0090     u32 : 32;
0091     struct {
0092         u64 wb;
0093         u64 wt;
0094     } addr[PCI_STD_NUM_BARS];
0095     u32 reserved[6];
0096 } __packed;
0097
0098 /* Query PCI function request */
0099 struct clp_req_query_pci {
0100     struct clp_req_hdr hdr;
0101     u32 fh;             /* function handle */
0102     u32 reserved2;
0103     u64 reserved3;
0104 } __packed;
0105
0106 /* Query PCI function response */
0107 struct clp_rsp_query_pci {
0108     struct clp_rsp_hdr hdr;
0109     u16 vfn;            /* virtual fn number */
0110     u16         :  3;
0111     u16 rid_avail       :  1;
0112     u16 is_physfn       :  1;
0113     u16 reserved1       :  1;
0114     u16 mio_addr_avail  :  1;
0115     u16 util_str_avail  :  1;   /* utility string available? */
0116     u16 pfgid       :  8;   /* pci function group id */
0117     u32 fid;            /* pci function id */
0118     u8 bar_size[PCI_STD_NUM_BARS];
0119     u16 pchid;
0120     __le32 bar[PCI_STD_NUM_BARS];
0121     u8 pfip[CLP_PFIP_NR_SEGMENTS];  /* pci function internal path */
0122     u16         : 12;
0123     u16 port        :  4;
0124     u8 fmb_len;
0125     u8 pft;             /* pci function type */
0126     u64 sdma;           /* start dma as */
0127     u64 edma;           /* end dma as */
0128 #define ZPCI_RID_MASK_DEVFN 0x00ff
0129     u16 rid;            /* BUS/DEVFN PCI address */
0130     u16 reserved0;
0131     u32 reserved[10];
0132     u32 uid;            /* user defined id */
0133     u8 util_str[CLP_UTIL_STR_LEN];  /* utility string */
0134     u32 reserved2[16];
0135     struct mio_info mio;
0136 } __packed;
0137
0138 /* Query PCI function group request */
0139 struct clp_req_query_pci_grp {
0140     struct clp_req_hdr hdr;
0141     u32 reserved2       : 24;
0142     u32 pfgid       :  8;   /* function group id */
0143     u32 reserved3;
0144     u64 reserved4;
0145 } __packed;
0146
0147 /* Query PCI function group response */
0148 struct clp_rsp_query_pci_grp {
0149     struct clp_rsp_hdr hdr;
0150     u16         :  4;
0151     u16 noi         : 12;   /* number of interrupts */
0152     u8 version;
0153     u8          :  6;
0154     u8 frame        :  1;
0155     u8 refresh      :  1;   /* TLB refresh mode */
0156     u16         :  3;
0157     u16 maxstbl     : 13;   /* Maximum store block size */
0158     u16 mui;
0159     u8 dtsm;            /* Supported DT mask */
0160     u8 reserved3;
0161     u16 maxfaal;
0162     u16         :  4;
0163     u16 dnoi        : 12;
0164     u16 maxcpu;
0165     u64 dasm;           /* dma address space mask */
0166     u64 msia;           /* MSI address */
0167     u64 reserved4;
0168     u64 reserved5;
0169 } __packed;
0170
0171 /* Set PCI function request */
0172 struct clp_req_set_pci {
0173     struct clp_req_hdr hdr;
0174     u32 fh;             /* function handle */
0175     u16 reserved2;
0176     u8 oc;              /* operation controls */
0177     u8 ndas;            /* number of dma spaces */
0178     u32 reserved3;
0179     u32 gisa;           /* GISA designation */
0180 } __packed;
0181
0182 /* Set PCI function response */
0183 struct clp_rsp_set_pci {
0184     struct clp_rsp_hdr hdr;
0185     u32 fh;             /* function handle */
0186     u32 reserved1;
0187     u64 reserved2;
0188     struct mio_info mio;
0189 } __packed;
0190
0191 /* Combined request/response block structures used by clp insn */
0192 struct clp_req_rsp_slpc_pci {
0193     struct clp_req_slpc request;
0194     struct clp_rsp_slpc_pci response;
0195 } __packed;
0196
0197 struct clp_req_rsp_list_pci {
0198     struct clp_req_list_pci request;
0199     struct clp_rsp_list_pci response;
0200 } __packed;
0201
0202 struct clp_req_rsp_set_pci {
0203     struct clp_req_set_pci request;
0204     struct clp_rsp_set_pci response;
0205 } __packed;
0206
0207 struct clp_req_rsp_query_pci {
0208     struct clp_req_query_pci request;
0209     struct clp_rsp_query_pci response;
0210 } __packed;
0211
0212 struct clp_req_rsp_query_pci_grp {
0213     struct clp_req_query_pci_grp request;
0214     struct clp_rsp_query_pci_grp response;
0215 } __packed;
0216
0217 #endif