powerpc/xmon/spu.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* SPU ELF support for BFD.
0003
0004    Copyright 2006 Free Software Foundation, Inc.
0005
0006    This file is part of GDB, GAS, and the GNU binutils.
0007
0008  */
0009
0010
0011 /* These two enums are from rel_apu/common/spu_asm_format.h */
0012 /* definition of instruction format */
0013 typedef enum {
0014   RRR,
0015   RI18,
0016   RI16,
0017   RI10,
0018   RI8,
0019   RI7,
0020   RR,
0021   LBT,
0022   LBTI,
0023   IDATA,
0024   UNKNOWN_IFORMAT
0025 } spu_iformat;
0026
0027 /* These values describe assembly instruction arguments.  They indicate
0028  * how to encode, range checking and which relocation to use. */
0029 typedef enum {
0030   A_T,  /* register at pos 0 */
0031   A_A,  /* register at pos 7 */
0032   A_B,  /* register at pos 14 */
0033   A_C,  /* register at pos 21 */
0034   A_S,  /* special purpose register at pos 7 */
0035   A_H,  /* channel register at pos 7 */
0036   A_P,  /* parenthesis, this has to separate regs from immediates */
0037   A_S3,
0038   A_S6,
0039   A_S7N,
0040   A_S7,
0041   A_U7A,
0042   A_U7B,
0043   A_S10B,
0044   A_S10,
0045   A_S11,
0046   A_S11I,
0047   A_S14,
0048   A_S16,
0049   A_S18,
0050   A_R18,
0051   A_U3,
0052   A_U5,
0053   A_U6,
0054   A_U7,
0055   A_U14,
0056   A_X16,
0057   A_U18,
0058   A_MAX
0059 } spu_aformat;
0060
0061 enum spu_insns {
0062 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
0063     TAG,
0064 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
0065     TAG,
0066 #include "spu-insns.h"
0067 #undef APUOP
0068 #undef APUOPFB
0069         M_SPU_MAX
0070 };
0071
0072 struct spu_opcode
0073 {
0074    spu_iformat insn_type;
0075    unsigned int opcode;
0076    char *mnemonic;
0077    int arg[5];
0078 };
0079
0080 #define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
0081 #define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
0082
0083 #define DECODE_INSN_RT(insn) (insn & 0x7f)
0084 #define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
0085 #define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
0086 #define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
0087
0088 #define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
0089 #define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
0090
0091 /* For branching, immediate loads, hbr and  lqa/stqa. */
0092 #define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
0093 #define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
0094
0095 /* for stop */
0096 #define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
0097
0098 /* For ila */
0099 #define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
0100 #define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
0101
0102 /* For rotate and shift and generate control mask */
0103 #define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
0104 #define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
0105
0106 /* For float <-> int conversion */
0107 #define DECODE_INSN_I8(insn)  SIGNED_EXTRACT(insn,8,14)
0108 #define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
0109
0110 /* For hbr  */
0111 #define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
0112 #define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
0113 #define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
0114 #define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
0115