powerpc/xmon/ppc.h

0001 /* ppc.h -- Header file for PowerPC opcode table
0002    Copyright (C) 1994-2016 Free Software Foundation, Inc.
0003    Written by Ian Lance Taylor, Cygnus Support
0004
0005 This file is part of GDB, GAS, and the GNU binutils.
0006
0007 GDB, GAS, and the GNU binutils are free software; you can redistribute
0008 them and/or modify them under the terms of the GNU General Public
0009 License as published by the Free Software Foundation; either version
0010 1, or (at your option) any later version.
0011
0012 GDB, GAS, and the GNU binutils are distributed in the hope that they
0013 will be useful, but WITHOUT ANY WARRANTY; without even the implied
0014 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
0015 the GNU General Public License for more details.
0016
0017 You should have received a copy of the GNU General Public License
0018 along with this file; see the file COPYING.  If not, write to the Free
0019 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
0020
0021 #ifndef PPC_H
0022 #define PPC_H
0023
0024 #ifdef __cplusplus
0025 extern "C" {
0026 #endif
0027
0028 typedef uint64_t ppc_cpu_t;
0029
0030 /* The opcode table is an array of struct powerpc_opcode.  */
0031
0032 struct powerpc_opcode
0033 {
0034   /* The opcode name.  */
0035   const char *name;
0036
0037   /* The opcode itself.  Those bits which will be filled in with
0038      operands are zeroes.  */
0039   unsigned long opcode;
0040
0041   /* The opcode mask.  This is used by the disassembler.  This is a
0042      mask containing ones indicating those bits which must match the
0043      opcode field, and zeroes indicating those bits which need not
0044      match (and are presumably filled in by operands).  */
0045   unsigned long mask;
0046
0047   /* One bit flags for the opcode.  These are used to indicate which
0048      specific processors support the instructions.  The defined values
0049      are listed below.  */
0050   ppc_cpu_t flags;
0051
0052   /* One bit flags for the opcode.  These are used to indicate which
0053      specific processors no longer support the instructions.  The defined
0054      values are listed below.  */
0055   ppc_cpu_t deprecated;
0056
0057   /* An array of operand codes.  Each code is an index into the
0058      operand table.  They appear in the order which the operands must
0059      appear in assembly code, and are terminated by a zero.  */
0060   unsigned char operands[8];
0061 };
0062
0063 /* The table itself is sorted by major opcode number, and is otherwise
0064    in the order in which the disassembler should consider
0065    instructions.  */
0066 extern const struct powerpc_opcode powerpc_opcodes[];
0067 extern const int powerpc_num_opcodes;
0068 extern const struct powerpc_opcode vle_opcodes[];
0069 extern const int vle_num_opcodes;
0070
0071 /* Values defined for the flags field of a struct powerpc_opcode.  */
0072
0073 /* Opcode is defined for the PowerPC architecture.  */
0074 #define PPC_OPCODE_PPC           1
0075
0076 /* Opcode is defined for the POWER (RS/6000) architecture.  */
0077 #define PPC_OPCODE_POWER         2
0078
0079 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
0080 #define PPC_OPCODE_POWER2        4
0081
0082 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
0083    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
0084    but it also supports many additional POWER instructions.  */
0085 #define PPC_OPCODE_601           8
0086
0087 /* Opcode is supported in both the Power and PowerPC architectures
0088    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
0089    the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
0090    and PPC_OPCODE_POWER2 because many instructions changed mnemonics
0091    between POWER and POWERPC.  */
0092 #define PPC_OPCODE_COMMON         0x10
0093
0094 /* Opcode is supported for any Power or PowerPC platform (this is
0095    for the assembler's -many option, and it eliminates duplicates).  */
0096 #define PPC_OPCODE_ANY            0x20
0097
0098 /* Opcode is only defined on 64 bit architectures.  */
0099 #define PPC_OPCODE_64             0x40
0100
0101 /* Opcode is supported as part of the 64-bit bridge.  */
0102 #define PPC_OPCODE_64_BRIDGE          0x80
0103
0104 /* Opcode is supported by Altivec Vector Unit */
0105 #define PPC_OPCODE_ALTIVEC       0x100
0106
0107 /* Opcode is supported by PowerPC 403 processor.  */
0108 #define PPC_OPCODE_403           0x200
0109
0110 /* Opcode is supported by PowerPC BookE processor.  */
0111 #define PPC_OPCODE_BOOKE         0x400
0112
0113 /* Opcode is supported by PowerPC 440 processor.  */
0114 #define PPC_OPCODE_440           0x800
0115
0116 /* Opcode is only supported by Power4 architecture.  */
0117 #define PPC_OPCODE_POWER4       0x1000
0118
0119 /* Opcode is only supported by Power7 architecture.  */
0120 #define PPC_OPCODE_POWER7       0x2000
0121
0122 /* Opcode is only supported by e500x2 Core.  */
0123 #define PPC_OPCODE_SPE          0x4000
0124
0125 /* Opcode is supported by e500x2 Integer select APU.  */
0126 #define PPC_OPCODE_ISEL         0x8000
0127
0128 /* Opcode is an e500 SPE floating point instruction.  */
0129 #define PPC_OPCODE_EFS         0x10000
0130
0131 /* Opcode is supported by branch locking APU.  */
0132 #define PPC_OPCODE_BRLOCK      0x20000
0133
0134 /* Opcode is supported by performance monitor APU.  */
0135 #define PPC_OPCODE_PMR         0x40000
0136
0137 /* Opcode is supported by cache locking APU.  */
0138 #define PPC_OPCODE_CACHELCK    0x80000
0139
0140 /* Opcode is supported by machine check APU.  */
0141 #define PPC_OPCODE_RFMCI      0x100000
0142
0143 /* Opcode is only supported by Power5 architecture.  */
0144 #define PPC_OPCODE_POWER5     0x200000
0145
0146 /* Opcode is supported by PowerPC e300 family.  */
0147 #define PPC_OPCODE_E300           0x400000
0148
0149 /* Opcode is only supported by Power6 architecture.  */
0150 #define PPC_OPCODE_POWER6     0x800000
0151
0152 /* Opcode is only supported by PowerPC Cell family.  */
0153 #define PPC_OPCODE_CELL      0x1000000
0154
0155 /* Opcode is supported by CPUs with paired singles support.  */
0156 #define PPC_OPCODE_PPCPS     0x2000000
0157
0158 /* Opcode is supported by Power E500MC */
0159 #define PPC_OPCODE_E500MC        0x4000000
0160
0161 /* Opcode is supported by PowerPC 405 processor.  */
0162 #define PPC_OPCODE_405       0x8000000
0163
0164 /* Opcode is supported by Vector-Scalar (VSX) Unit */
0165 #define PPC_OPCODE_VSX      0x10000000
0166
0167 /* Opcode is supported by A2.  */
0168 #define PPC_OPCODE_A2       0x20000000
0169
0170 /* Opcode is supported by PowerPC 476 processor.  */
0171 #define PPC_OPCODE_476      0x40000000
0172
0173 /* Opcode is supported by AppliedMicro Titan core */
0174 #define PPC_OPCODE_TITAN        0x80000000
0175
0176 /* Opcode which is supported by the e500 family */
0177 #define PPC_OPCODE_E500        0x100000000ull
0178
0179 /* Opcode is supported by Extended Altivec Vector Unit */
0180 #define PPC_OPCODE_ALTIVEC2    0x200000000ull
0181
0182 /* Opcode is supported by Power E6500 */
0183 #define PPC_OPCODE_E6500       0x400000000ull
0184
0185 /* Opcode is supported by Thread management APU */
0186 #define PPC_OPCODE_TMR         0x800000000ull
0187
0188 /* Opcode which is supported by the VLE extension.  */
0189 #define PPC_OPCODE_VLE        0x1000000000ull
0190
0191 /* Opcode is only supported by Power8 architecture.  */
0192 #define PPC_OPCODE_POWER8     0x2000000000ull
0193
0194 /* Opcode which is supported by the Hardware Transactional Memory extension.  */
0195 /* Currently, this is the same as the POWER8 mask.  If another cpu comes out
0196    that isn't a superset of POWER8, we can define this to its own mask.  */
0197 #define PPC_OPCODE_HTM        PPC_OPCODE_POWER8
0198
0199 /* Opcode is supported by ppc750cl.  */
0200 #define PPC_OPCODE_750        0x4000000000ull
0201
0202 /* Opcode is supported by ppc7450.  */
0203 #define PPC_OPCODE_7450       0x8000000000ull
0204
0205 /* Opcode is supported by ppc821/850/860.  */
0206 #define PPC_OPCODE_860        0x10000000000ull
0207
0208 /* Opcode is only supported by Power9 architecture.  */
0209 #define PPC_OPCODE_POWER9     0x20000000000ull
0210
0211 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08.  */
0212 #define PPC_OPCODE_VSX3       0x40000000000ull
0213
0214   /* Opcode is supported by e200z4.  */
0215 #define PPC_OPCODE_E200Z4     0x80000000000ull
0216
0217 /* A macro to extract the major opcode from an instruction.  */
0218 #define PPC_OP(i) (((i) >> 26) & 0x3f)
0219
0220 /* A macro to determine if the instruction is a 2-byte VLE insn.  */
0221 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
0222
0223 /* A macro to extract the major opcode from a VLE instruction.  */
0224 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
0225
0226 /* A macro to convert a VLE opcode to a VLE opcode segment.  */
0227 #define VLE_OP_TO_SEG(i) ((i) >> 1)
0228
0229 /* The operands table is an array of struct powerpc_operand.  */
0230
0231 struct powerpc_operand
0232 {
0233   /* A bitmask of bits in the operand.  */
0234   unsigned int bitm;
0235
0236   /* The shift operation to be applied to the operand.  No shift
0237      is made if this is zero.  For positive values, the operand
0238      is shifted left by SHIFT.  For negative values, the operand
0239      is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
0240      that BITM and SHIFT cannot be used to determine where the
0241      operand goes in the insn.  */
0242   int shift;
0243
0244   /* Insertion function.  This is used by the assembler.  To insert an
0245      operand value into an instruction, check this field.
0246
0247      If it is NULL, execute
0248      if (o->shift >= 0)
0249        i |= (op & o->bitm) << o->shift;
0250      else
0251        i |= (op & o->bitm) >> -o->shift;
0252      (i is the instruction which we are filling in, o is a pointer to
0253      this structure, and op is the operand value).
0254
0255      If this field is not NULL, then simply call it with the
0256      instruction and the operand value.  It will return the new value
0257      of the instruction.  If the ERRMSG argument is not NULL, then if
0258      the operand value is illegal, *ERRMSG will be set to a warning
0259      string (the operand will be inserted in any case).  If the
0260      operand value is legal, *ERRMSG will be unchanged (most operands
0261      can accept any value).  */
0262   unsigned long (*insert)
0263     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
0264
0265   /* Extraction function.  This is used by the disassembler.  To
0266      extract this operand type from an instruction, check this field.
0267
0268      If it is NULL, compute
0269      if (o->shift >= 0)
0270        op = (i >> o->shift) & o->bitm;
0271      else
0272        op = (i << -o->shift) & o->bitm;
0273      if ((o->flags & PPC_OPERAND_SIGNED) != 0)
0274        sign_extend (op);
0275      (i is the instruction, o is a pointer to this structure, and op
0276      is the result).
0277
0278      If this field is not NULL, then simply call it with the
0279      instruction value.  It will return the value of the operand.  If
0280      the INVALID argument is not NULL, *INVALID will be set to
0281      non-zero if this operand type can not actually be extracted from
0282      this operand (i.e., the instruction does not match).  If the
0283      operand is valid, *INVALID will not be changed.  */
0284   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
0285
0286   /* One bit syntax flags.  */
0287   unsigned long flags;
0288 };
0289
0290 /* Elements in the table are retrieved by indexing with values from
0291    the operands field of the powerpc_opcodes table.  */
0292
0293 extern const struct powerpc_operand powerpc_operands[];
0294 extern const unsigned int num_powerpc_operands;
0295
0296 /* Use with the shift field of a struct powerpc_operand to indicate
0297      that BITM and SHIFT cannot be used to determine where the operand
0298      goes in the insn.  */
0299 #define PPC_OPSHIFT_INV (-1U << 31)
0300
0301 /* Values defined for the flags field of a struct powerpc_operand.  */
0302
0303 /* This operand takes signed values.  */
0304 #define PPC_OPERAND_SIGNED (0x1)
0305
0306 /* This operand takes signed values, but also accepts a full positive
0307    range of values when running in 32 bit mode.  That is, if bits is
0308    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
0309    this flag is ignored.  */
0310 #define PPC_OPERAND_SIGNOPT (0x2)
0311
0312 /* This operand does not actually exist in the assembler input.  This
0313    is used to support extended mnemonics such as mr, for which two
0314    operands fields are identical.  The assembler should call the
0315    insert function with any op value.  The disassembler should call
0316    the extract function, ignore the return value, and check the value
0317    placed in the valid argument.  */
0318 #define PPC_OPERAND_FAKE (0x4)
0319
0320 /* The next operand should be wrapped in parentheses rather than
0321    separated from this one by a comma.  This is used for the load and
0322    store instructions which want their operands to look like
0323        reg,displacement(reg)
0324    */
0325 #define PPC_OPERAND_PARENS (0x8)
0326
0327 /* This operand may use the symbolic names for the CR fields, which
0328    are
0329        lt  0    gt  1   eq  2   so  3   un  3
0330        cr0 0    cr1 1   cr2 2   cr3 3
0331        cr4 4    cr5 5   cr6 6   cr7 7
0332    These may be combined arithmetically, as in cr2*4+gt.  These are
0333    only supported on the PowerPC, not the POWER.  */
0334 #define PPC_OPERAND_CR_BIT (0x10)
0335
0336 /* This operand names a register.  The disassembler uses this to print
0337    register names with a leading 'r'.  */
0338 #define PPC_OPERAND_GPR (0x20)
0339
0340 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
0341 #define PPC_OPERAND_GPR_0 (0x40)
0342
0343 /* This operand names a floating point register.  The disassembler
0344    prints these with a leading 'f'.  */
0345 #define PPC_OPERAND_FPR (0x80)
0346
0347 /* This operand is a relative branch displacement.  The disassembler
0348    prints these symbolically if possible.  */
0349 #define PPC_OPERAND_RELATIVE (0x100)
0350
0351 /* This operand is an absolute branch address.  The disassembler
0352    prints these symbolically if possible.  */
0353 #define PPC_OPERAND_ABSOLUTE (0x200)
0354
0355 /* This operand is optional, and is zero if omitted.  This is used for
0356    example, in the optional BF field in the comparison instructions.  The
0357    assembler must count the number of operands remaining on the line,
0358    and the number of operands remaining for the opcode, and decide
0359    whether this operand is present or not.  The disassembler should
0360    print this operand out only if it is not zero.  */
0361 #define PPC_OPERAND_OPTIONAL (0x400)
0362
0363 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
0364    is omitted, then for the next operand use this operand value plus
0365    1, ignoring the next operand field for the opcode.  This wretched
0366    hack is needed because the Power rotate instructions can take
0367    either 4 or 5 operands.  The disassembler should print this operand
0368    out regardless of the PPC_OPERAND_OPTIONAL field.  */
0369 #define PPC_OPERAND_NEXT (0x800)
0370
0371 /* This operand should be regarded as a negative number for the
0372    purposes of overflow checking (i.e., the normal most negative
0373    number is disallowed and one more than the normal most positive
0374    number is allowed).  This flag will only be set for a signed
0375    operand.  */
0376 #define PPC_OPERAND_NEGATIVE (0x1000)
0377
0378 /* This operand names a vector unit register.  The disassembler
0379    prints these with a leading 'v'.  */
0380 #define PPC_OPERAND_VR (0x2000)
0381
0382 /* This operand is for the DS field in a DS form instruction.  */
0383 #define PPC_OPERAND_DS (0x4000)
0384
0385 /* This operand is for the DQ field in a DQ form instruction.  */
0386 #define PPC_OPERAND_DQ (0x8000)
0387
0388 /* Valid range of operand is 0..n rather than 0..n-1.  */
0389 #define PPC_OPERAND_PLUS1 (0x10000)
0390
0391 /* Xilinx APU and FSL related operands */
0392 #define PPC_OPERAND_FSL (0x20000)
0393 #define PPC_OPERAND_FCR (0x40000)
0394 #define PPC_OPERAND_UDI (0x80000)
0395
0396 /* This operand names a vector-scalar unit register.  The disassembler
0397    prints these with a leading 'vs'.  */
0398 #define PPC_OPERAND_VSR (0x100000)
0399
0400 /* This is a CR FIELD that does not use symbolic names.  */
0401 #define PPC_OPERAND_CR_REG (0x200000)
0402
0403 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
0404    is omitted, then the value it should use for the operand is stored
0405    in the SHIFT field of the immediatly following operand field.  */
0406 #define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
0407
0408 /* This flag is only used with PPC_OPERAND_OPTIONAL.  The operand is
0409    only optional when generating 32-bit code.  */
0410 #define PPC_OPERAND_OPTIONAL32 (0x800000)
0411
0412 /* The POWER and PowerPC assemblers use a few macros.  We keep them
0413    with the operands table for simplicity.  The macro table is an
0414    array of struct powerpc_macro.  */
0415
0416 struct powerpc_macro
0417 {
0418   /* The macro name.  */
0419   const char *name;
0420
0421   /* The number of operands the macro takes.  */
0422   unsigned int operands;
0423
0424   /* One bit flags for the opcode.  These are used to indicate which
0425      specific processors support the instructions.  The values are the
0426      same as those for the struct powerpc_opcode flags field.  */
0427   ppc_cpu_t flags;
0428
0429   /* A format string to turn the macro into a normal instruction.
0430      Each %N in the string is replaced with operand number N (zero
0431      based).  */
0432   const char *format;
0433 };
0434
0435 extern const struct powerpc_macro powerpc_macros[];
0436 extern const int powerpc_num_macros;
0437
0438 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
0439
0440 static inline long
0441 ppc_optional_operand_value (const struct powerpc_operand *operand)
0442 {
0443   if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
0444     return (operand+1)->shift;
0445   return 0;
0446 }
0447
0448 #ifdef __cplusplus
0449 }
0450 #endif
0451
0452 #endif /* PPC_H */