sysdev/xive/xive-internal.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2016,2017 IBM Corporation.
0004  */
0005 #ifndef __XIVE_INTERNAL_H
0006 #define __XIVE_INTERNAL_H
0007
0008 /*
0009  * A "disabled" interrupt should never fire, to catch problems
0010  * we set its logical number to this
0011  */
0012 #define XIVE_BAD_IRQ        0x7fffffff
0013 #define XIVE_MAX_IRQ        (XIVE_BAD_IRQ - 1)
0014
0015 /* Each CPU carry one of these with various per-CPU state */
0016 struct xive_cpu {
0017 #ifdef CONFIG_SMP
0018     /* HW irq number and data of IPI */
0019     u32 hw_ipi;
0020     struct xive_irq_data ipi_data;
0021 #endif /* CONFIG_SMP */
0022
0023     int chip_id;
0024
0025     /* Queue datas. Only one is populated */
0026 #define XIVE_MAX_QUEUES 8
0027     struct xive_q queue[XIVE_MAX_QUEUES];
0028
0029     /*
0030      * Pending mask. Each bit corresponds to a priority that
0031      * potentially has pending interrupts.
0032      */
0033     u8 pending_prio;
0034
0035     /* Cache of HW CPPR */
0036     u8 cppr;
0037 };
0038
0039 /* Backend ops */
0040 struct xive_ops {
0041     int (*populate_irq_data)(u32 hw_irq, struct xive_irq_data *data);
0042     int     (*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
0043     int (*get_irq_config)(u32 hw_irq, u32 *target, u8 *prio,
0044                   u32 *sw_irq);
0045     int (*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
0046     void    (*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
0047     void    (*prepare_cpu)(unsigned int cpu, struct xive_cpu *xc);
0048     void    (*setup_cpu)(unsigned int cpu, struct xive_cpu *xc);
0049     void    (*teardown_cpu)(unsigned int cpu, struct xive_cpu *xc);
0050     bool    (*match)(struct device_node *np);
0051     void    (*shutdown)(void);
0052
0053     void    (*update_pending)(struct xive_cpu *xc);
0054     void    (*sync_source)(u32 hw_irq);
0055     u64 (*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);
0056 #ifdef CONFIG_SMP
0057     int (*get_ipi)(unsigned int cpu, struct xive_cpu *xc);
0058     void    (*put_ipi)(unsigned int cpu, struct xive_cpu *xc);
0059 #endif
0060     int (*debug_show)(struct seq_file *m, void *private);
0061     int (*debug_create)(struct dentry *xive_dir);
0062     const char *name;
0063 };
0064
0065 bool xive_core_init(struct device_node *np, const struct xive_ops *ops,
0066             void __iomem *area, u32 offset, u8 max_prio);
0067 __be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift);
0068 int xive_core_debug_init(void);
0069
0070 static inline u32 xive_alloc_order(u32 queue_shift)
0071 {
0072     return (queue_shift > PAGE_SHIFT) ? (queue_shift - PAGE_SHIFT) : 0;
0073 }
0074
0075 extern bool xive_cmdline_disabled;
0076 extern bool xive_has_save_restore;
0077
0078 #endif /*  __XIVE_INTERNAL_H */