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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * MPIC timer driver
0004  *
0005  * Copyright 2013 Freescale Semiconductor, Inc.
0006  * Author: Dongsheng Wang <Dongsheng.Wang@freescale.com>
0007  *     Li Yang <leoli@freescale.com>
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/module.h>
0013 #include <linux/errno.h>
0014 #include <linux/mm.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/slab.h>
0017 #include <linux/of.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_device.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/syscore_ops.h>
0022 #include <sysdev/fsl_soc.h>
0023 #include <asm/io.h>
0024 
0025 #include <asm/mpic_timer.h>
0026 
0027 #define FSL_GLOBAL_TIMER        0x1
0028 
0029 /* Clock Ratio
0030  * Divide by 64 0x00000300
0031  * Divide by 32 0x00000200
0032  * Divide by 16 0x00000100
0033  * Divide by  8 0x00000000 (Hardware default div)
0034  */
0035 #define MPIC_TIMER_TCR_CLKDIV       0x00000300
0036 
0037 #define MPIC_TIMER_TCR_ROVR_OFFSET  24
0038 
0039 #define TIMER_STOP          0x80000000
0040 #define GTCCR_TOG           0x80000000
0041 #define TIMERS_PER_GROUP        4
0042 #define MAX_TICKS           (~0U >> 1)
0043 #define MAX_TICKS_CASCADE       (~0U)
0044 #define TIMER_OFFSET(num)       (1 << (TIMERS_PER_GROUP - 1 - num))
0045 
0046 struct timer_regs {
0047     u32 gtccr;
0048     u32 res0[3];
0049     u32 gtbcr;
0050     u32 res1[3];
0051     u32 gtvpr;
0052     u32 res2[3];
0053     u32 gtdr;
0054     u32 res3[3];
0055 };
0056 
0057 struct cascade_priv {
0058     u32 tcr_value;          /* TCR register: CASC & ROVR value */
0059     unsigned int cascade_map;   /* cascade map */
0060     unsigned int timer_num;     /* cascade control timer */
0061 };
0062 
0063 struct timer_group_priv {
0064     struct timer_regs __iomem   *regs;
0065     struct mpic_timer       timer[TIMERS_PER_GROUP];
0066     struct list_head        node;
0067     unsigned int            timerfreq;
0068     unsigned int            idle;
0069     unsigned int            flags;
0070     spinlock_t          lock;
0071     void __iomem            *group_tcr;
0072 };
0073 
0074 static struct cascade_priv cascade_timer[] = {
0075     /* cascade timer 0 and 1 */
0076     {0x1, 0xc, 0x1},
0077     /* cascade timer 1 and 2 */
0078     {0x2, 0x6, 0x2},
0079     /* cascade timer 2 and 3 */
0080     {0x4, 0x3, 0x3}
0081 };
0082 
0083 static LIST_HEAD(timer_group_list);
0084 
0085 static void convert_ticks_to_time(struct timer_group_priv *priv,
0086         const u64 ticks, time64_t *time)
0087 {
0088     *time = (u64)div_u64(ticks, priv->timerfreq);
0089 }
0090 
0091 /* the time set by the user is converted to "ticks" */
0092 static int convert_time_to_ticks(struct timer_group_priv *priv,
0093         time64_t time, u64 *ticks)
0094 {
0095     u64 max_value;      /* prevent u64 overflow */
0096 
0097     max_value = div_u64(ULLONG_MAX, priv->timerfreq);
0098 
0099     if (time > max_value)
0100         return -EINVAL;
0101 
0102     *ticks = (u64)time * (u64)priv->timerfreq;
0103 
0104     return 0;
0105 }
0106 
0107 /* detect whether there is a cascade timer available */
0108 static struct mpic_timer *detect_idle_cascade_timer(
0109                     struct timer_group_priv *priv)
0110 {
0111     struct cascade_priv *casc_priv;
0112     unsigned int map;
0113     unsigned int array_size = ARRAY_SIZE(cascade_timer);
0114     unsigned int num;
0115     unsigned int i;
0116     unsigned long flags;
0117 
0118     casc_priv = cascade_timer;
0119     for (i = 0; i < array_size; i++) {
0120         spin_lock_irqsave(&priv->lock, flags);
0121         map = casc_priv->cascade_map & priv->idle;
0122         if (map == casc_priv->cascade_map) {
0123             num = casc_priv->timer_num;
0124             priv->timer[num].cascade_handle = casc_priv;
0125 
0126             /* set timer busy */
0127             priv->idle &= ~casc_priv->cascade_map;
0128             spin_unlock_irqrestore(&priv->lock, flags);
0129             return &priv->timer[num];
0130         }
0131         spin_unlock_irqrestore(&priv->lock, flags);
0132         casc_priv++;
0133     }
0134 
0135     return NULL;
0136 }
0137 
0138 static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
0139         unsigned int num)
0140 {
0141     struct cascade_priv *casc_priv;
0142     u32 tcr;
0143     u32 tmp_ticks;
0144     u32 rem_ticks;
0145 
0146     /* set group tcr reg for cascade */
0147     casc_priv = priv->timer[num].cascade_handle;
0148     if (!casc_priv)
0149         return -EINVAL;
0150 
0151     tcr = casc_priv->tcr_value |
0152         (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
0153     setbits32(priv->group_tcr, tcr);
0154 
0155     tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
0156 
0157     out_be32(&priv->regs[num].gtccr, 0);
0158     out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP);
0159 
0160     out_be32(&priv->regs[num - 1].gtccr, 0);
0161     out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);
0162 
0163     return 0;
0164 }
0165 
0166 static struct mpic_timer *get_cascade_timer(struct timer_group_priv *priv,
0167                     u64 ticks)
0168 {
0169     struct mpic_timer *allocated_timer;
0170 
0171     /* Two cascade timers: Support the maximum time */
0172     const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE;
0173     int ret;
0174 
0175     if (ticks > max_ticks)
0176         return NULL;
0177 
0178     /* detect idle timer */
0179     allocated_timer = detect_idle_cascade_timer(priv);
0180     if (!allocated_timer)
0181         return NULL;
0182 
0183     /* set ticks to timer */
0184     ret = set_cascade_timer(priv, ticks, allocated_timer->num);
0185     if (ret < 0)
0186         return NULL;
0187 
0188     return allocated_timer;
0189 }
0190 
0191 static struct mpic_timer *get_timer(time64_t time)
0192 {
0193     struct timer_group_priv *priv;
0194     struct mpic_timer *timer;
0195 
0196     u64 ticks;
0197     unsigned int num;
0198     unsigned int i;
0199     unsigned long flags;
0200     int ret;
0201 
0202     list_for_each_entry(priv, &timer_group_list, node) {
0203         ret = convert_time_to_ticks(priv, time, &ticks);
0204         if (ret < 0)
0205             return NULL;
0206 
0207         if (ticks > MAX_TICKS) {
0208             if (!(priv->flags & FSL_GLOBAL_TIMER))
0209                 return NULL;
0210 
0211             timer = get_cascade_timer(priv, ticks);
0212             if (!timer)
0213                 continue;
0214 
0215             return timer;
0216         }
0217 
0218         for (i = 0; i < TIMERS_PER_GROUP; i++) {
0219             /* one timer: Reverse allocation */
0220             num = TIMERS_PER_GROUP - 1 - i;
0221             spin_lock_irqsave(&priv->lock, flags);
0222             if (priv->idle & (1 << i)) {
0223                 /* set timer busy */
0224                 priv->idle &= ~(1 << i);
0225                 /* set ticks & stop timer */
0226                 out_be32(&priv->regs[num].gtbcr,
0227                     ticks | TIMER_STOP);
0228                 out_be32(&priv->regs[num].gtccr, 0);
0229                 priv->timer[num].cascade_handle = NULL;
0230                 spin_unlock_irqrestore(&priv->lock, flags);
0231                 return &priv->timer[num];
0232             }
0233             spin_unlock_irqrestore(&priv->lock, flags);
0234         }
0235     }
0236 
0237     return NULL;
0238 }
0239 
0240 /**
0241  * mpic_start_timer - start hardware timer
0242  * @handle: the timer to be started.
0243  *
0244  * It will do ->fn(->dev) callback from the hardware interrupt at
0245  * the 'time64_t' point in the future.
0246  */
0247 void mpic_start_timer(struct mpic_timer *handle)
0248 {
0249     struct timer_group_priv *priv = container_of(handle,
0250             struct timer_group_priv, timer[handle->num]);
0251 
0252     clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
0253 }
0254 EXPORT_SYMBOL(mpic_start_timer);
0255 
0256 /**
0257  * mpic_stop_timer - stop hardware timer
0258  * @handle: the timer to be stopped
0259  *
0260  * The timer periodically generates an interrupt. Unless user stops the timer.
0261  */
0262 void mpic_stop_timer(struct mpic_timer *handle)
0263 {
0264     struct timer_group_priv *priv = container_of(handle,
0265             struct timer_group_priv, timer[handle->num]);
0266     struct cascade_priv *casc_priv;
0267 
0268     setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
0269 
0270     casc_priv = priv->timer[handle->num].cascade_handle;
0271     if (casc_priv) {
0272         out_be32(&priv->regs[handle->num].gtccr, 0);
0273         out_be32(&priv->regs[handle->num - 1].gtccr, 0);
0274     } else {
0275         out_be32(&priv->regs[handle->num].gtccr, 0);
0276     }
0277 }
0278 EXPORT_SYMBOL(mpic_stop_timer);
0279 
0280 /**
0281  * mpic_get_remain_time - get timer time
0282  * @handle: the timer to be selected.
0283  * @time: time for timer
0284  *
0285  * Query timer remaining time.
0286  */
0287 void mpic_get_remain_time(struct mpic_timer *handle, time64_t *time)
0288 {
0289     struct timer_group_priv *priv = container_of(handle,
0290             struct timer_group_priv, timer[handle->num]);
0291     struct cascade_priv *casc_priv;
0292 
0293     u64 ticks;
0294     u32 tmp_ticks;
0295 
0296     casc_priv = priv->timer[handle->num].cascade_handle;
0297     if (casc_priv) {
0298         tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
0299         tmp_ticks &= ~GTCCR_TOG;
0300         ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
0301         tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
0302         ticks += tmp_ticks;
0303     } else {
0304         ticks = in_be32(&priv->regs[handle->num].gtccr);
0305         ticks &= ~GTCCR_TOG;
0306     }
0307 
0308     convert_ticks_to_time(priv, ticks, time);
0309 }
0310 EXPORT_SYMBOL(mpic_get_remain_time);
0311 
0312 /**
0313  * mpic_free_timer - free hardware timer
0314  * @handle: the timer to be removed.
0315  *
0316  * Free the timer.
0317  *
0318  * Note: can not be used in interrupt context.
0319  */
0320 void mpic_free_timer(struct mpic_timer *handle)
0321 {
0322     struct timer_group_priv *priv = container_of(handle,
0323             struct timer_group_priv, timer[handle->num]);
0324 
0325     struct cascade_priv *casc_priv;
0326     unsigned long flags;
0327 
0328     mpic_stop_timer(handle);
0329 
0330     casc_priv = priv->timer[handle->num].cascade_handle;
0331 
0332     free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);
0333 
0334     spin_lock_irqsave(&priv->lock, flags);
0335     if (casc_priv) {
0336         u32 tcr;
0337         tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
0338                     MPIC_TIMER_TCR_ROVR_OFFSET);
0339         clrbits32(priv->group_tcr, tcr);
0340         priv->idle |= casc_priv->cascade_map;
0341         priv->timer[handle->num].cascade_handle = NULL;
0342     } else {
0343         priv->idle |= TIMER_OFFSET(handle->num);
0344     }
0345     spin_unlock_irqrestore(&priv->lock, flags);
0346 }
0347 EXPORT_SYMBOL(mpic_free_timer);
0348 
0349 /**
0350  * mpic_request_timer - get a hardware timer
0351  * @fn: interrupt handler function
0352  * @dev: callback function of the data
0353  * @time: time for timer
0354  *
0355  * This executes the "request_irq", returning NULL
0356  * else "handle" on success.
0357  */
0358 struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
0359                       time64_t time)
0360 {
0361     struct mpic_timer *allocated_timer;
0362     int ret;
0363 
0364     if (list_empty(&timer_group_list))
0365         return NULL;
0366 
0367     if (time < 0)
0368         return NULL;
0369 
0370     allocated_timer = get_timer(time);
0371     if (!allocated_timer)
0372         return NULL;
0373 
0374     ret = request_irq(allocated_timer->irq, fn,
0375             IRQF_TRIGGER_LOW, "global-timer", dev);
0376     if (ret) {
0377         mpic_free_timer(allocated_timer);
0378         return NULL;
0379     }
0380 
0381     allocated_timer->dev = dev;
0382 
0383     return allocated_timer;
0384 }
0385 EXPORT_SYMBOL(mpic_request_timer);
0386 
0387 static int __init timer_group_get_freq(struct device_node *np,
0388             struct timer_group_priv *priv)
0389 {
0390     u32 div;
0391 
0392     if (priv->flags & FSL_GLOBAL_TIMER) {
0393         struct device_node *dn;
0394 
0395         dn = of_find_compatible_node(NULL, NULL, "fsl,mpic");
0396         if (dn) {
0397             of_property_read_u32(dn, "clock-frequency",
0398                     &priv->timerfreq);
0399             of_node_put(dn);
0400         }
0401     }
0402 
0403     if (priv->timerfreq <= 0)
0404         return -EINVAL;
0405 
0406     if (priv->flags & FSL_GLOBAL_TIMER) {
0407         div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8;
0408         priv->timerfreq /= div;
0409     }
0410 
0411     return 0;
0412 }
0413 
0414 static int __init timer_group_get_irq(struct device_node *np,
0415         struct timer_group_priv *priv)
0416 {
0417     const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
0418     const u32 *p;
0419     u32 offset;
0420     u32 count;
0421 
0422     unsigned int i;
0423     unsigned int j;
0424     unsigned int irq_index = 0;
0425     unsigned int irq;
0426     int len;
0427 
0428     p = of_get_property(np, "fsl,available-ranges", &len);
0429     if (p && len % (2 * sizeof(u32)) != 0) {
0430         pr_err("%pOF: malformed available-ranges property.\n", np);
0431         return -EINVAL;
0432     }
0433 
0434     if (!p) {
0435         p = all_timer;
0436         len = sizeof(all_timer);
0437     }
0438 
0439     len /= 2 * sizeof(u32);
0440 
0441     for (i = 0; i < len; i++) {
0442         offset = p[i * 2];
0443         count = p[i * 2 + 1];
0444         for (j = 0; j < count; j++) {
0445             irq = irq_of_parse_and_map(np, irq_index);
0446             if (!irq) {
0447                 pr_err("%pOF: irq parse and map failed.\n", np);
0448                 return -EINVAL;
0449             }
0450 
0451             /* Set timer idle */
0452             priv->idle |= TIMER_OFFSET((offset + j));
0453             priv->timer[offset + j].irq = irq;
0454             priv->timer[offset + j].num = offset + j;
0455             irq_index++;
0456         }
0457     }
0458 
0459     return 0;
0460 }
0461 
0462 static void __init timer_group_init(struct device_node *np)
0463 {
0464     struct timer_group_priv *priv;
0465     unsigned int i = 0;
0466     int ret;
0467 
0468     priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL);
0469     if (!priv) {
0470         pr_err("%pOF: cannot allocate memory for group.\n", np);
0471         return;
0472     }
0473 
0474     if (of_device_is_compatible(np, "fsl,mpic-global-timer"))
0475         priv->flags |= FSL_GLOBAL_TIMER;
0476 
0477     priv->regs = of_iomap(np, i++);
0478     if (!priv->regs) {
0479         pr_err("%pOF: cannot ioremap timer register address.\n", np);
0480         goto out;
0481     }
0482 
0483     if (priv->flags & FSL_GLOBAL_TIMER) {
0484         priv->group_tcr = of_iomap(np, i++);
0485         if (!priv->group_tcr) {
0486             pr_err("%pOF: cannot ioremap tcr address.\n", np);
0487             goto out;
0488         }
0489     }
0490 
0491     ret = timer_group_get_freq(np, priv);
0492     if (ret < 0) {
0493         pr_err("%pOF: cannot get timer frequency.\n", np);
0494         goto out;
0495     }
0496 
0497     ret = timer_group_get_irq(np, priv);
0498     if (ret < 0) {
0499         pr_err("%pOF: cannot get timer irqs.\n", np);
0500         goto out;
0501     }
0502 
0503     spin_lock_init(&priv->lock);
0504 
0505     /* Init FSL timer hardware */
0506     if (priv->flags & FSL_GLOBAL_TIMER)
0507         setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
0508 
0509     list_add_tail(&priv->node, &timer_group_list);
0510 
0511     return;
0512 
0513 out:
0514     if (priv->regs)
0515         iounmap(priv->regs);
0516 
0517     if (priv->group_tcr)
0518         iounmap(priv->group_tcr);
0519 
0520     kfree(priv);
0521 }
0522 
0523 static void mpic_timer_resume(void)
0524 {
0525     struct timer_group_priv *priv;
0526 
0527     list_for_each_entry(priv, &timer_group_list, node) {
0528         /* Init FSL timer hardware */
0529         if (priv->flags & FSL_GLOBAL_TIMER)
0530             setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
0531     }
0532 }
0533 
0534 static const struct of_device_id mpic_timer_ids[] = {
0535     { .compatible = "fsl,mpic-global-timer", },
0536     {},
0537 };
0538 
0539 static struct syscore_ops mpic_timer_syscore_ops = {
0540     .resume = mpic_timer_resume,
0541 };
0542 
0543 static int __init mpic_timer_init(void)
0544 {
0545     struct device_node *np = NULL;
0546 
0547     for_each_matching_node(np, mpic_timer_ids)
0548         timer_group_init(np);
0549 
0550     register_syscore_ops(&mpic_timer_syscore_ops);
0551 
0552     if (list_empty(&timer_group_list))
0553         return -ENODEV;
0554 
0555     return 0;
0556 }
0557 subsys_initcall(mpic_timer_init);
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