powerpc/sysdev/ipic.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * IPIC private definitions and structure.
0004  *
0005  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
0006  *
0007  * Copyright 2005 Freescale Semiconductor, Inc
0008  */
0009 #ifndef __IPIC_H__
0010 #define __IPIC_H__
0011
0012 #include <asm/ipic.h>
0013
0014 #define NR_IPIC_INTS 128
0015
0016 /* External IRQS */
0017 #define IPIC_IRQ_EXT0 48
0018 #define IPIC_IRQ_EXT1 17
0019 #define IPIC_IRQ_EXT7 23
0020
0021 /* Default Priority Registers */
0022 #define IPIC_PRIORITY_DEFAULT 0x05309770
0023
0024 /* System Global Interrupt Configuration Register */
0025 #define SICFR_IPSA  0x00010000
0026 #define SICFR_IPSB  0x00020000
0027 #define SICFR_IPSC  0x00040000
0028 #define SICFR_IPSD  0x00080000
0029 #define SICFR_MPSA  0x00200000
0030 #define SICFR_MPSB  0x00400000
0031
0032 /* System External Interrupt Mask Register */
0033 #define SEMSR_SIRQ0 0x00008000
0034
0035 /* System Error Control Register */
0036 #define SERCR_MCPR  0x00000001
0037
0038 struct ipic {
0039     volatile u32 __iomem    *regs;
0040
0041     /* The remapper for this IPIC */
0042     struct irq_domain       *irqhost;
0043 };
0044
0045 struct ipic_info {
0046     u8  ack;        /* pending register offset from base if the irq
0047                    supports ack operation */
0048     u8  mask;       /* mask register offset from base */
0049     u8  prio;       /* priority register offset from base */
0050     u8  force;      /* force register offset from base */
0051     u8  bit;        /* register bit position (as per doc)
0052                    bit mask = 1 << (31 - bit) */
0053     u8  prio_mask;  /* priority mask value */
0054 };
0055
0056 #endif /* __IPIC_H__ */