powerpc/sysdev/fsl_soc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __PPC_FSL_SOC_H
0003 #define __PPC_FSL_SOC_H
0004 #ifdef __KERNEL__
0005
0006 #include <asm/mmu.h>
0007
0008 struct spi_device;
0009
0010 extern phys_addr_t get_immrbase(void);
0011 #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
0012 extern u32 get_brgfreq(void);
0013 extern u32 get_baudrate(void);
0014 #else
0015 static inline u32 get_brgfreq(void) { return -1; }
0016 static inline u32 get_baudrate(void) { return -1; }
0017 #endif
0018 extern u32 fsl_get_sys_freq(void);
0019
0020 struct spi_board_info;
0021 struct device_node;
0022
0023 /* The different ports that the DIU can be connected to */
0024 enum fsl_diu_monitor_port {
0025     FSL_DIU_PORT_DVI,   /* DVI */
0026     FSL_DIU_PORT_LVDS,  /* Single-link LVDS */
0027     FSL_DIU_PORT_DLVDS  /* Dual-link LVDS */
0028 };
0029
0030 struct platform_diu_data_ops {
0031     u32 (*get_pixel_format)(enum fsl_diu_monitor_port port,
0032         unsigned int bpp);
0033     void (*set_gamma_table)(enum fsl_diu_monitor_port port,
0034         char *gamma_table_base);
0035     void (*set_monitor_port)(enum fsl_diu_monitor_port port);
0036     void (*set_pixel_clock)(unsigned int pixclock);
0037     enum fsl_diu_monitor_port (*valid_monitor_port)
0038         (enum fsl_diu_monitor_port port);
0039     void (*release_bootmem)(void);
0040 };
0041
0042 extern struct platform_diu_data_ops diu_ops;
0043
0044 void __noreturn fsl_hv_restart(char *cmd);
0045 void __noreturn fsl_hv_halt(void);
0046
0047 #endif
0048 #endif