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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale MPC85xx/MPC86xx RapidIO RMU support
0004  *
0005  * Copyright 2009 Sysgo AG
0006  * Thomas Moll <thomas.moll@sysgo.com>
0007  * - fixed maintenance access routines, check for aligned access
0008  *
0009  * Copyright 2009 Integrated Device Technology, Inc.
0010  * Alex Bounine <alexandre.bounine@idt.com>
0011  * - Added Port-Write message handling
0012  * - Added Machine Check exception handling
0013  *
0014  * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
0015  * Zhang Wei <wei.zhang@freescale.com>
0016  * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
0017  * Liu Gang <Gang.Liu@freescale.com>
0018  *
0019  * Copyright 2005 MontaVista Software, Inc.
0020  * Matt Porter <mporter@kernel.crashing.org>
0021  */
0022 
0023 #include <linux/types.h>
0024 #include <linux/dma-mapping.h>
0025 #include <linux/interrupt.h>
0026 #include <linux/of_irq.h>
0027 #include <linux/of_platform.h>
0028 #include <linux/slab.h>
0029 
0030 #include "fsl_rio.h"
0031 
0032 #define GET_RMM_HANDLE(mport) \
0033         (((struct rio_priv *)(mport->priv))->rmm_handle)
0034 
0035 /* RapidIO definition irq, which read from OF-tree */
0036 #define IRQ_RIO_PW(m)       (((struct fsl_rio_pw *)(m))->pwirq)
0037 #define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq)
0038 #define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq)
0039 #define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq)
0040 
0041 #define RIO_MIN_TX_RING_SIZE    2
0042 #define RIO_MAX_TX_RING_SIZE    2048
0043 #define RIO_MIN_RX_RING_SIZE    2
0044 #define RIO_MAX_RX_RING_SIZE    2048
0045 
0046 #define RIO_IPWMR_SEN       0x00100000
0047 #define RIO_IPWMR_QFIE      0x00000100
0048 #define RIO_IPWMR_EIE       0x00000020
0049 #define RIO_IPWMR_CQ        0x00000002
0050 #define RIO_IPWMR_PWE       0x00000001
0051 
0052 #define RIO_IPWSR_QF        0x00100000
0053 #define RIO_IPWSR_TE        0x00000080
0054 #define RIO_IPWSR_QFI       0x00000010
0055 #define RIO_IPWSR_PWD       0x00000008
0056 #define RIO_IPWSR_PWB       0x00000004
0057 
0058 #define RIO_EPWISR      0x10010
0059 /* EPWISR Error match value */
0060 #define RIO_EPWISR_PINT1    0x80000000
0061 #define RIO_EPWISR_PINT2    0x40000000
0062 #define RIO_EPWISR_MU       0x00000002
0063 #define RIO_EPWISR_PW       0x00000001
0064 
0065 #define IPWSR_CLEAR     0x98
0066 #define OMSR_CLEAR      0x1cb3
0067 #define IMSR_CLEAR      0x491
0068 #define IDSR_CLEAR      0x91
0069 #define ODSR_CLEAR      0x1c00
0070 #define LTLEECSR_ENABLE_ALL 0xFFC000FC
0071 #define RIO_LTLEECSR        0x060c
0072 
0073 #define RIO_IM0SR       0x64
0074 #define RIO_IM1SR       0x164
0075 #define RIO_OM0SR       0x4
0076 #define RIO_OM1SR       0x104
0077 
0078 #define RIO_DBELL_WIN_SIZE  0x1000
0079 
0080 #define RIO_MSG_OMR_MUI     0x00000002
0081 #define RIO_MSG_OSR_TE      0x00000080
0082 #define RIO_MSG_OSR_QOI     0x00000020
0083 #define RIO_MSG_OSR_QFI     0x00000010
0084 #define RIO_MSG_OSR_MUB     0x00000004
0085 #define RIO_MSG_OSR_EOMI    0x00000002
0086 #define RIO_MSG_OSR_QEI     0x00000001
0087 
0088 #define RIO_MSG_IMR_MI      0x00000002
0089 #define RIO_MSG_ISR_TE      0x00000080
0090 #define RIO_MSG_ISR_QFI     0x00000010
0091 #define RIO_MSG_ISR_DIQI    0x00000001
0092 
0093 #define RIO_MSG_DESC_SIZE   32
0094 #define RIO_MSG_BUFFER_SIZE 4096
0095 
0096 #define DOORBELL_DMR_DI     0x00000002
0097 #define DOORBELL_DSR_TE     0x00000080
0098 #define DOORBELL_DSR_QFI    0x00000010
0099 #define DOORBELL_DSR_DIQI   0x00000001
0100 
0101 #define DOORBELL_MESSAGE_SIZE   0x08
0102 
0103 static DEFINE_SPINLOCK(fsl_rio_doorbell_lock);
0104 
0105 struct rio_msg_regs {
0106     u32 omr;
0107     u32 osr;
0108     u32 pad1;
0109     u32 odqdpar;
0110     u32 pad2;
0111     u32 osar;
0112     u32 odpr;
0113     u32 odatr;
0114     u32 odcr;
0115     u32 pad3;
0116     u32 odqepar;
0117     u32 pad4[13];
0118     u32 imr;
0119     u32 isr;
0120     u32 pad5;
0121     u32 ifqdpar;
0122     u32 pad6;
0123     u32 ifqepar;
0124 };
0125 
0126 struct rio_dbell_regs {
0127     u32 odmr;
0128     u32 odsr;
0129     u32 pad1[4];
0130     u32 oddpr;
0131     u32 oddatr;
0132     u32 pad2[3];
0133     u32 odretcr;
0134     u32 pad3[12];
0135     u32 dmr;
0136     u32 dsr;
0137     u32 pad4;
0138     u32 dqdpar;
0139     u32 pad5;
0140     u32 dqepar;
0141 };
0142 
0143 struct rio_pw_regs {
0144     u32 pwmr;
0145     u32 pwsr;
0146     u32 epwqbar;
0147     u32 pwqbar;
0148 };
0149 
0150 
0151 struct rio_tx_desc {
0152     u32 pad1;
0153     u32 saddr;
0154     u32 dport;
0155     u32 dattr;
0156     u32 pad2;
0157     u32 pad3;
0158     u32 dwcnt;
0159     u32 pad4;
0160 };
0161 
0162 struct rio_msg_tx_ring {
0163     void *virt;
0164     dma_addr_t phys;
0165     void *virt_buffer[RIO_MAX_TX_RING_SIZE];
0166     dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
0167     int tx_slot;
0168     int size;
0169     void *dev_id;
0170 };
0171 
0172 struct rio_msg_rx_ring {
0173     void *virt;
0174     dma_addr_t phys;
0175     void *virt_buffer[RIO_MAX_RX_RING_SIZE];
0176     int rx_slot;
0177     int size;
0178     void *dev_id;
0179 };
0180 
0181 struct fsl_rmu {
0182     struct rio_msg_regs __iomem *msg_regs;
0183     struct rio_msg_tx_ring msg_tx_ring;
0184     struct rio_msg_rx_ring msg_rx_ring;
0185     int txirq;
0186     int rxirq;
0187 };
0188 
0189 struct rio_dbell_msg {
0190     u16 pad1;
0191     u16 tid;
0192     u16 sid;
0193     u16 info;
0194 };
0195 
0196 /**
0197  * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
0198  * @irq: Linux interrupt number
0199  * @dev_instance: Pointer to interrupt-specific data
0200  *
0201  * Handles outbound message interrupts. Executes a register outbound
0202  * mailbox event handler and acks the interrupt occurrence.
0203  */
0204 static irqreturn_t
0205 fsl_rio_tx_handler(int irq, void *dev_instance)
0206 {
0207     int osr;
0208     struct rio_mport *port = (struct rio_mport *)dev_instance;
0209     struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
0210 
0211     osr = in_be32(&rmu->msg_regs->osr);
0212 
0213     if (osr & RIO_MSG_OSR_TE) {
0214         pr_info("RIO: outbound message transmission error\n");
0215         out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE);
0216         goto out;
0217     }
0218 
0219     if (osr & RIO_MSG_OSR_QOI) {
0220         pr_info("RIO: outbound message queue overflow\n");
0221         out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI);
0222         goto out;
0223     }
0224 
0225     if (osr & RIO_MSG_OSR_EOMI) {
0226         u32 dqp = in_be32(&rmu->msg_regs->odqdpar);
0227         int slot = (dqp - rmu->msg_tx_ring.phys) >> 5;
0228         if (port->outb_msg[0].mcback != NULL) {
0229             port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id,
0230                     -1,
0231                     slot);
0232         }
0233         /* Ack the end-of-message interrupt */
0234         out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI);
0235     }
0236 
0237 out:
0238     return IRQ_HANDLED;
0239 }
0240 
0241 /**
0242  * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
0243  * @irq: Linux interrupt number
0244  * @dev_instance: Pointer to interrupt-specific data
0245  *
0246  * Handles inbound message interrupts. Executes a registered inbound
0247  * mailbox event handler and acks the interrupt occurrence.
0248  */
0249 static irqreturn_t
0250 fsl_rio_rx_handler(int irq, void *dev_instance)
0251 {
0252     int isr;
0253     struct rio_mport *port = (struct rio_mport *)dev_instance;
0254     struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
0255 
0256     isr = in_be32(&rmu->msg_regs->isr);
0257 
0258     if (isr & RIO_MSG_ISR_TE) {
0259         pr_info("RIO: inbound message reception error\n");
0260         out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE);
0261         goto out;
0262     }
0263 
0264     /* XXX Need to check/dispatch until queue empty */
0265     if (isr & RIO_MSG_ISR_DIQI) {
0266         /*
0267         * Can receive messages for any mailbox/letter to that
0268         * mailbox destination. So, make the callback with an
0269         * unknown/invalid mailbox number argument.
0270         */
0271         if (port->inb_msg[0].mcback != NULL)
0272             port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id,
0273                 -1,
0274                 -1);
0275 
0276         /* Ack the queueing interrupt */
0277         out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI);
0278     }
0279 
0280 out:
0281     return IRQ_HANDLED;
0282 }
0283 
0284 /**
0285  * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
0286  * @irq: Linux interrupt number
0287  * @dev_instance: Pointer to interrupt-specific data
0288  *
0289  * Handles doorbell interrupts. Parses a list of registered
0290  * doorbell event handlers and executes a matching event handler.
0291  */
0292 static irqreturn_t
0293 fsl_rio_dbell_handler(int irq, void *dev_instance)
0294 {
0295     int dsr;
0296     struct fsl_rio_dbell *fsl_dbell = (struct fsl_rio_dbell *)dev_instance;
0297     int i;
0298 
0299     dsr = in_be32(&fsl_dbell->dbell_regs->dsr);
0300 
0301     if (dsr & DOORBELL_DSR_TE) {
0302         pr_info("RIO: doorbell reception error\n");
0303         out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_TE);
0304         goto out;
0305     }
0306 
0307     if (dsr & DOORBELL_DSR_QFI) {
0308         pr_info("RIO: doorbell queue full\n");
0309         out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_QFI);
0310     }
0311 
0312     /* XXX Need to check/dispatch until queue empty */
0313     if (dsr & DOORBELL_DSR_DIQI) {
0314         struct rio_dbell_msg *dmsg =
0315             fsl_dbell->dbell_ring.virt +
0316             (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff);
0317         struct rio_dbell *dbell;
0318         int found = 0;
0319 
0320         pr_debug
0321             ("RIO: processing doorbell,"
0322             " sid %2.2x tid %2.2x info %4.4x\n",
0323             dmsg->sid, dmsg->tid, dmsg->info);
0324 
0325         for (i = 0; i < MAX_PORT_NUM; i++) {
0326             if (fsl_dbell->mport[i]) {
0327                 list_for_each_entry(dbell,
0328                     &fsl_dbell->mport[i]->dbells, node) {
0329                     if ((dbell->res->start
0330                         <= dmsg->info)
0331                         && (dbell->res->end
0332                         >= dmsg->info)) {
0333                         found = 1;
0334                         break;
0335                     }
0336                 }
0337                 if (found && dbell->dinb) {
0338                     dbell->dinb(fsl_dbell->mport[i],
0339                         dbell->dev_id, dmsg->sid,
0340                         dmsg->tid,
0341                         dmsg->info);
0342                     break;
0343                 }
0344             }
0345         }
0346 
0347         if (!found) {
0348             pr_debug
0349                 ("RIO: spurious doorbell,"
0350                 " sid %2.2x tid %2.2x info %4.4x\n",
0351                 dmsg->sid, dmsg->tid,
0352                 dmsg->info);
0353         }
0354         setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
0355         out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
0356     }
0357 
0358 out:
0359     return IRQ_HANDLED;
0360 }
0361 
0362 void msg_unit_error_handler(void)
0363 {
0364 
0365     /*XXX: Error recovery is not implemented, we just clear errors */
0366     out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
0367 
0368     out_be32((u32 *)(rmu_regs_win + RIO_IM0SR), IMSR_CLEAR);
0369     out_be32((u32 *)(rmu_regs_win + RIO_IM1SR), IMSR_CLEAR);
0370     out_be32((u32 *)(rmu_regs_win + RIO_OM0SR), OMSR_CLEAR);
0371     out_be32((u32 *)(rmu_regs_win + RIO_OM1SR), OMSR_CLEAR);
0372 
0373     out_be32(&dbell->dbell_regs->odsr, ODSR_CLEAR);
0374     out_be32(&dbell->dbell_regs->dsr, IDSR_CLEAR);
0375 
0376     out_be32(&pw->pw_regs->pwsr, IPWSR_CLEAR);
0377 }
0378 
0379 /**
0380  * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
0381  * @irq: Linux interrupt number
0382  * @dev_instance: Pointer to interrupt-specific data
0383  *
0384  * Handles port write interrupts. Parses a list of registered
0385  * port write event handlers and executes a matching event handler.
0386  */
0387 static irqreturn_t
0388 fsl_rio_port_write_handler(int irq, void *dev_instance)
0389 {
0390     u32 ipwmr, ipwsr;
0391     struct fsl_rio_pw *pw = (struct fsl_rio_pw *)dev_instance;
0392     u32 epwisr, tmp;
0393 
0394     epwisr = in_be32(rio_regs_win + RIO_EPWISR);
0395     if (!(epwisr & RIO_EPWISR_PW))
0396         goto pw_done;
0397 
0398     ipwmr = in_be32(&pw->pw_regs->pwmr);
0399     ipwsr = in_be32(&pw->pw_regs->pwsr);
0400 
0401 #ifdef DEBUG_PW
0402     pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
0403     if (ipwsr & RIO_IPWSR_QF)
0404         pr_debug(" QF");
0405     if (ipwsr & RIO_IPWSR_TE)
0406         pr_debug(" TE");
0407     if (ipwsr & RIO_IPWSR_QFI)
0408         pr_debug(" QFI");
0409     if (ipwsr & RIO_IPWSR_PWD)
0410         pr_debug(" PWD");
0411     if (ipwsr & RIO_IPWSR_PWB)
0412         pr_debug(" PWB");
0413     pr_debug(" )\n");
0414 #endif
0415     /* Schedule deferred processing if PW was received */
0416     if (ipwsr & RIO_IPWSR_QFI) {
0417         /* Save PW message (if there is room in FIFO),
0418          * otherwise discard it.
0419          */
0420         if (kfifo_avail(&pw->pw_fifo) >= RIO_PW_MSG_SIZE) {
0421             pw->port_write_msg.msg_count++;
0422             kfifo_in(&pw->pw_fifo, pw->port_write_msg.virt,
0423                  RIO_PW_MSG_SIZE);
0424         } else {
0425             pw->port_write_msg.discard_count++;
0426             pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
0427                  pw->port_write_msg.discard_count);
0428         }
0429         /* Clear interrupt and issue Clear Queue command. This allows
0430          * another port-write to be received.
0431          */
0432         out_be32(&pw->pw_regs->pwsr,    RIO_IPWSR_QFI);
0433         out_be32(&pw->pw_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
0434 
0435         schedule_work(&pw->pw_work);
0436     }
0437 
0438     if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
0439         pw->port_write_msg.err_count++;
0440         pr_debug("RIO: Port-Write Transaction Err (%d)\n",
0441              pw->port_write_msg.err_count);
0442         /* Clear Transaction Error: port-write controller should be
0443          * disabled when clearing this error
0444          */
0445         out_be32(&pw->pw_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
0446         out_be32(&pw->pw_regs->pwsr,    RIO_IPWSR_TE);
0447         out_be32(&pw->pw_regs->pwmr, ipwmr);
0448     }
0449 
0450     if (ipwsr & RIO_IPWSR_PWD) {
0451         pw->port_write_msg.discard_count++;
0452         pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
0453              pw->port_write_msg.discard_count);
0454         out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_PWD);
0455     }
0456 
0457 pw_done:
0458     if (epwisr & RIO_EPWISR_PINT1) {
0459         tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
0460         pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
0461         fsl_rio_port_error_handler(0);
0462     }
0463 
0464     if (epwisr & RIO_EPWISR_PINT2) {
0465         tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
0466         pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
0467         fsl_rio_port_error_handler(1);
0468     }
0469 
0470     if (epwisr & RIO_EPWISR_MU) {
0471         tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
0472         pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
0473         msg_unit_error_handler();
0474     }
0475 
0476     return IRQ_HANDLED;
0477 }
0478 
0479 static void fsl_pw_dpc(struct work_struct *work)
0480 {
0481     struct fsl_rio_pw *pw = container_of(work, struct fsl_rio_pw, pw_work);
0482     union rio_pw_msg msg_buffer;
0483     int i;
0484 
0485     /*
0486      * Process port-write messages
0487      */
0488     while (kfifo_out_spinlocked(&pw->pw_fifo, (unsigned char *)&msg_buffer,
0489              RIO_PW_MSG_SIZE, &pw->pw_fifo_lock)) {
0490 #ifdef DEBUG_PW
0491         {
0492         u32 i;
0493         pr_debug("%s : Port-Write Message:", __func__);
0494         for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
0495             if ((i%4) == 0)
0496                 pr_debug("\n0x%02x: 0x%08x", i*4,
0497                      msg_buffer.raw[i]);
0498             else
0499                 pr_debug(" 0x%08x", msg_buffer.raw[i]);
0500         }
0501         pr_debug("\n");
0502         }
0503 #endif
0504         /* Pass the port-write message to RIO core for processing */
0505         for (i = 0; i < MAX_PORT_NUM; i++) {
0506             if (pw->mport[i])
0507                 rio_inb_pwrite_handler(pw->mport[i],
0508                                &msg_buffer);
0509         }
0510     }
0511 }
0512 
0513 /**
0514  * fsl_rio_pw_enable - enable/disable port-write interface init
0515  * @mport: Master port implementing the port write unit
0516  * @enable:    1=enable; 0=disable port-write message handling
0517  */
0518 int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
0519 {
0520     u32 rval;
0521 
0522     rval = in_be32(&pw->pw_regs->pwmr);
0523 
0524     if (enable)
0525         rval |= RIO_IPWMR_PWE;
0526     else
0527         rval &= ~RIO_IPWMR_PWE;
0528 
0529     out_be32(&pw->pw_regs->pwmr, rval);
0530 
0531     return 0;
0532 }
0533 
0534 /**
0535  * fsl_rio_port_write_init - MPC85xx port write interface init
0536  * @mport: Master port implementing the port write unit
0537  *
0538  * Initializes port write unit hardware and DMA buffer
0539  * ring. Called from fsl_rio_setup(). Returns %0 on success
0540  * or %-ENOMEM on failure.
0541  */
0542 
0543 int fsl_rio_port_write_init(struct fsl_rio_pw *pw)
0544 {
0545     int rc = 0;
0546 
0547     /* Following configurations require a disabled port write controller */
0548     out_be32(&pw->pw_regs->pwmr,
0549          in_be32(&pw->pw_regs->pwmr) & ~RIO_IPWMR_PWE);
0550 
0551     /* Initialize port write */
0552     pw->port_write_msg.virt = dma_alloc_coherent(pw->dev,
0553                     RIO_PW_MSG_SIZE,
0554                     &pw->port_write_msg.phys, GFP_KERNEL);
0555     if (!pw->port_write_msg.virt) {
0556         pr_err("RIO: unable allocate port write queue\n");
0557         return -ENOMEM;
0558     }
0559 
0560     pw->port_write_msg.err_count = 0;
0561     pw->port_write_msg.discard_count = 0;
0562 
0563     /* Point dequeue/enqueue pointers at first entry */
0564     out_be32(&pw->pw_regs->epwqbar, 0);
0565     out_be32(&pw->pw_regs->pwqbar, (u32) pw->port_write_msg.phys);
0566 
0567     pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
0568          in_be32(&pw->pw_regs->epwqbar),
0569          in_be32(&pw->pw_regs->pwqbar));
0570 
0571     /* Clear interrupt status IPWSR */
0572     out_be32(&pw->pw_regs->pwsr,
0573          (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
0574 
0575     /* Configure port write controller for snooping enable all reporting,
0576        clear queue full */
0577     out_be32(&pw->pw_regs->pwmr,
0578          RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
0579 
0580 
0581     /* Hook up port-write handler */
0582     rc = request_irq(IRQ_RIO_PW(pw), fsl_rio_port_write_handler,
0583             IRQF_SHARED, "port-write", (void *)pw);
0584     if (rc < 0) {
0585         pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
0586         goto err_out;
0587     }
0588     /* Enable Error Interrupt */
0589     out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
0590 
0591     INIT_WORK(&pw->pw_work, fsl_pw_dpc);
0592     spin_lock_init(&pw->pw_fifo_lock);
0593     if (kfifo_alloc(&pw->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
0594         pr_err("FIFO allocation failed\n");
0595         rc = -ENOMEM;
0596         goto err_out_irq;
0597     }
0598 
0599     pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
0600          in_be32(&pw->pw_regs->pwmr),
0601          in_be32(&pw->pw_regs->pwsr));
0602 
0603     return rc;
0604 
0605 err_out_irq:
0606     free_irq(IRQ_RIO_PW(pw), (void *)pw);
0607 err_out:
0608     dma_free_coherent(pw->dev, RIO_PW_MSG_SIZE,
0609         pw->port_write_msg.virt,
0610         pw->port_write_msg.phys);
0611     return rc;
0612 }
0613 
0614 /**
0615  * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
0616  * @mport: RapidIO master port info
0617  * @index: ID of RapidIO interface
0618  * @destid: Destination ID of target device
0619  * @data: 16-bit info field of RapidIO doorbell message
0620  *
0621  * Sends a MPC85xx doorbell message. Returns %0 on success or
0622  * %-EINVAL on failure.
0623  */
0624 int fsl_rio_doorbell_send(struct rio_mport *mport,
0625                 int index, u16 destid, u16 data)
0626 {
0627     unsigned long flags;
0628 
0629     pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
0630          index, destid, data);
0631 
0632     spin_lock_irqsave(&fsl_rio_doorbell_lock, flags);
0633 
0634     /* In the serial version silicons, such as MPC8548, MPC8641,
0635      * below operations is must be.
0636      */
0637     out_be32(&dbell->dbell_regs->odmr, 0x00000000);
0638     out_be32(&dbell->dbell_regs->odretcr, 0x00000004);
0639     out_be32(&dbell->dbell_regs->oddpr, destid << 16);
0640     out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data);
0641     out_be32(&dbell->dbell_regs->odmr, 0x00000001);
0642 
0643     spin_unlock_irqrestore(&fsl_rio_doorbell_lock, flags);
0644 
0645     return 0;
0646 }
0647 
0648 /**
0649  * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
0650  * @mport: Master port with outbound message queue
0651  * @rdev: Target of outbound message
0652  * @mbox: Outbound mailbox
0653  * @buffer: Message to add to outbound queue
0654  * @len: Length of message
0655  *
0656  * Adds the @buffer message to the MPC85xx outbound message queue. Returns
0657  * %0 on success or %-EINVAL on failure.
0658  */
0659 int
0660 fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
0661             void *buffer, size_t len)
0662 {
0663     struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
0664     u32 omr;
0665     struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt
0666                     + rmu->msg_tx_ring.tx_slot;
0667     int ret = 0;
0668 
0669     pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
0670          "%p len %8.8zx\n", rdev->destid, mbox, buffer, len);
0671     if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
0672         ret = -EINVAL;
0673         goto out;
0674     }
0675 
0676     /* Copy and clear rest of buffer */
0677     memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer,
0678             len);
0679     if (len < (RIO_MAX_MSG_SIZE - 4))
0680         memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot]
0681                 + len, 0, RIO_MAX_MSG_SIZE - len);
0682 
0683     /* Set mbox field for message, and set destid */
0684     desc->dport = (rdev->destid << 16) | (mbox & 0x3);
0685 
0686     /* Enable EOMI interrupt and priority */
0687     desc->dattr = 0x28000000 | ((mport->index) << 20);
0688 
0689     /* Set transfer size aligned to next power of 2 (in double words) */
0690     desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
0691 
0692     /* Set snooping and source buffer address */
0693     desc->saddr = 0x00000004
0694         | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot];
0695 
0696     /* Increment enqueue pointer */
0697     omr = in_be32(&rmu->msg_regs->omr);
0698     out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
0699 
0700     /* Go to next descriptor */
0701     if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size)
0702         rmu->msg_tx_ring.tx_slot = 0;
0703 
0704 out:
0705     return ret;
0706 }
0707 
0708 /**
0709  * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
0710  * @mport: Master port implementing the outbound message unit
0711  * @dev_id: Device specific pointer to pass on event
0712  * @mbox: Mailbox to open
0713  * @entries: Number of entries in the outbound mailbox ring
0714  *
0715  * Initializes buffer ring, request the outbound message interrupt,
0716  * and enables the outbound message unit. Returns %0 on success and
0717  * %-EINVAL or %-ENOMEM on failure.
0718  */
0719 int
0720 fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
0721 {
0722     int i, j, rc = 0;
0723     struct rio_priv *priv = mport->priv;
0724     struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
0725 
0726     if ((entries < RIO_MIN_TX_RING_SIZE) ||
0727         (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
0728         rc = -EINVAL;
0729         goto out;
0730     }
0731 
0732     /* Initialize shadow copy ring */
0733     rmu->msg_tx_ring.dev_id = dev_id;
0734     rmu->msg_tx_ring.size = entries;
0735 
0736     for (i = 0; i < rmu->msg_tx_ring.size; i++) {
0737         rmu->msg_tx_ring.virt_buffer[i] =
0738             dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
0739                 &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
0740         if (!rmu->msg_tx_ring.virt_buffer[i]) {
0741             rc = -ENOMEM;
0742             for (j = 0; j < rmu->msg_tx_ring.size; j++)
0743                 if (rmu->msg_tx_ring.virt_buffer[j])
0744                     dma_free_coherent(priv->dev,
0745                             RIO_MSG_BUFFER_SIZE,
0746                             rmu->msg_tx_ring.
0747                             virt_buffer[j],
0748                             rmu->msg_tx_ring.
0749                             phys_buffer[j]);
0750             goto out;
0751         }
0752     }
0753 
0754     /* Initialize outbound message descriptor ring */
0755     rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
0756                            rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
0757                            &rmu->msg_tx_ring.phys,
0758                            GFP_KERNEL);
0759     if (!rmu->msg_tx_ring.virt) {
0760         rc = -ENOMEM;
0761         goto out_dma;
0762     }
0763     rmu->msg_tx_ring.tx_slot = 0;
0764 
0765     /* Point dequeue/enqueue pointers at first entry in ring */
0766     out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys);
0767     out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys);
0768 
0769     /* Configure for snooping */
0770     out_be32(&rmu->msg_regs->osar, 0x00000004);
0771 
0772     /* Clear interrupt status */
0773     out_be32(&rmu->msg_regs->osr, 0x000000b3);
0774 
0775     /* Hook up outbound message handler */
0776     rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
0777              "msg_tx", (void *)mport);
0778     if (rc < 0)
0779         goto out_irq;
0780 
0781     /*
0782      * Configure outbound message unit
0783      *      Snooping
0784      *      Interrupts (all enabled, except QEIE)
0785      *      Chaining mode
0786      *      Disable
0787      */
0788     out_be32(&rmu->msg_regs->omr, 0x00100220);
0789 
0790     /* Set number of entries */
0791     out_be32(&rmu->msg_regs->omr,
0792          in_be32(&rmu->msg_regs->omr) |
0793          ((get_bitmask_order(entries) - 2) << 12));
0794 
0795     /* Now enable the unit */
0796     out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1);
0797 
0798 out:
0799     return rc;
0800 
0801 out_irq:
0802     dma_free_coherent(priv->dev,
0803         rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
0804         rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
0805 
0806 out_dma:
0807     for (i = 0; i < rmu->msg_tx_ring.size; i++)
0808         dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
0809         rmu->msg_tx_ring.virt_buffer[i],
0810         rmu->msg_tx_ring.phys_buffer[i]);
0811 
0812     return rc;
0813 }
0814 
0815 /**
0816  * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
0817  * @mport: Master port implementing the outbound message unit
0818  * @mbox: Mailbox to close
0819  *
0820  * Disables the outbound message unit, free all buffers, and
0821  * frees the outbound message interrupt.
0822  */
0823 void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
0824 {
0825     struct rio_priv *priv = mport->priv;
0826     struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
0827 
0828     /* Disable inbound message unit */
0829     out_be32(&rmu->msg_regs->omr, 0);
0830 
0831     /* Free ring */
0832     dma_free_coherent(priv->dev,
0833     rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
0834     rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
0835 
0836     /* Free interrupt */
0837     free_irq(IRQ_RIO_TX(mport), (void *)mport);
0838 }
0839 
0840 /**
0841  * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
0842  * @mport: Master port implementing the inbound message unit
0843  * @dev_id: Device specific pointer to pass on event
0844  * @mbox: Mailbox to open
0845  * @entries: Number of entries in the inbound mailbox ring
0846  *
0847  * Initializes buffer ring, request the inbound message interrupt,
0848  * and enables the inbound message unit. Returns %0 on success
0849  * and %-EINVAL or %-ENOMEM on failure.
0850  */
0851 int
0852 fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
0853 {
0854     int i, rc = 0;
0855     struct rio_priv *priv = mport->priv;
0856     struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
0857 
0858     if ((entries < RIO_MIN_RX_RING_SIZE) ||
0859         (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
0860         rc = -EINVAL;
0861         goto out;
0862     }
0863 
0864     /* Initialize client buffer ring */
0865     rmu->msg_rx_ring.dev_id = dev_id;
0866     rmu->msg_rx_ring.size = entries;
0867     rmu->msg_rx_ring.rx_slot = 0;
0868     for (i = 0; i < rmu->msg_rx_ring.size; i++)
0869         rmu->msg_rx_ring.virt_buffer[i] = NULL;
0870 
0871     /* Initialize inbound message ring */
0872     rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
0873                 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
0874                 &rmu->msg_rx_ring.phys, GFP_KERNEL);
0875     if (!rmu->msg_rx_ring.virt) {
0876         rc = -ENOMEM;
0877         goto out;
0878     }
0879 
0880     /* Point dequeue/enqueue pointers at first entry in ring */
0881     out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys);
0882     out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys);
0883 
0884     /* Clear interrupt status */
0885     out_be32(&rmu->msg_regs->isr, 0x00000091);
0886 
0887     /* Hook up inbound message handler */
0888     rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
0889              "msg_rx", (void *)mport);
0890     if (rc < 0) {
0891         dma_free_coherent(priv->dev,
0892             rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
0893             rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
0894         goto out;
0895     }
0896 
0897     /*
0898      * Configure inbound message unit:
0899      *      Snooping
0900      *      4KB max message size
0901      *      Unmask all interrupt sources
0902      *      Disable
0903      */
0904     out_be32(&rmu->msg_regs->imr, 0x001b0060);
0905 
0906     /* Set number of queue entries */
0907     setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
0908 
0909     /* Now enable the unit */
0910     setbits32(&rmu->msg_regs->imr, 0x1);
0911 
0912 out:
0913     return rc;
0914 }
0915 
0916 /**
0917  * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
0918  * @mport: Master port implementing the inbound message unit
0919  * @mbox: Mailbox to close
0920  *
0921  * Disables the inbound message unit, free all buffers, and
0922  * frees the inbound message interrupt.
0923  */
0924 void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
0925 {
0926     struct rio_priv *priv = mport->priv;
0927     struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
0928 
0929     /* Disable inbound message unit */
0930     out_be32(&rmu->msg_regs->imr, 0);
0931 
0932     /* Free ring */
0933     dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
0934     rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
0935 
0936     /* Free interrupt */
0937     free_irq(IRQ_RIO_RX(mport), (void *)mport);
0938 }
0939 
0940 /**
0941  * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
0942  * @mport: Master port implementing the inbound message unit
0943  * @mbox: Inbound mailbox number
0944  * @buf: Buffer to add to inbound queue
0945  *
0946  * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
0947  * %0 on success or %-EINVAL on failure.
0948  */
0949 int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
0950 {
0951     int rc = 0;
0952     struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
0953 
0954     pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
0955          rmu->msg_rx_ring.rx_slot);
0956 
0957     if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) {
0958         printk(KERN_ERR
0959             "RIO: error adding inbound buffer %d, buffer exists\n",
0960             rmu->msg_rx_ring.rx_slot);
0961         rc = -EINVAL;
0962         goto out;
0963     }
0964 
0965     rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf;
0966     if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size)
0967         rmu->msg_rx_ring.rx_slot = 0;
0968 
0969 out:
0970     return rc;
0971 }
0972 
0973 /**
0974  * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
0975  * @mport: Master port implementing the inbound message unit
0976  * @mbox: Inbound mailbox number
0977  *
0978  * Gets the next available inbound message from the inbound message queue.
0979  * A pointer to the message is returned on success or NULL on failure.
0980  */
0981 void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
0982 {
0983     struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
0984     u32 phys_buf;
0985     void *virt_buf;
0986     void *buf = NULL;
0987     int buf_idx;
0988 
0989     phys_buf = in_be32(&rmu->msg_regs->ifqdpar);
0990 
0991     /* If no more messages, then bail out */
0992     if (phys_buf == in_be32(&rmu->msg_regs->ifqepar))
0993         goto out2;
0994 
0995     virt_buf = rmu->msg_rx_ring.virt + (phys_buf
0996                         - rmu->msg_rx_ring.phys);
0997     buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
0998     buf = rmu->msg_rx_ring.virt_buffer[buf_idx];
0999 
1000     if (!buf) {
1001         printk(KERN_ERR
1002             "RIO: inbound message copy failed, no buffers\n");
1003         goto out1;
1004     }
1005 
1006     /* Copy max message size, caller is expected to allocate that big */
1007     memcpy(buf, virt_buf, RIO_MAX_MSG_SIZE);
1008 
1009     /* Clear the available buffer */
1010     rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
1011 
1012 out1:
1013     setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
1014 
1015 out2:
1016     return buf;
1017 }
1018 
1019 /**
1020  * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1021  * @mport: Master port implementing the inbound doorbell unit
1022  *
1023  * Initializes doorbell unit hardware and inbound DMA buffer
1024  * ring. Called from fsl_rio_setup(). Returns %0 on success
1025  * or %-ENOMEM on failure.
1026  */
1027 int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell)
1028 {
1029     int rc = 0;
1030 
1031     /* Initialize inbound doorbells */
1032     dbell->dbell_ring.virt = dma_alloc_coherent(dbell->dev, 512 *
1033         DOORBELL_MESSAGE_SIZE, &dbell->dbell_ring.phys, GFP_KERNEL);
1034     if (!dbell->dbell_ring.virt) {
1035         printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1036         rc = -ENOMEM;
1037         goto out;
1038     }
1039 
1040     /* Point dequeue/enqueue pointers at first entry in ring */
1041     out_be32(&dbell->dbell_regs->dqdpar, (u32) dbell->dbell_ring.phys);
1042     out_be32(&dbell->dbell_regs->dqepar, (u32) dbell->dbell_ring.phys);
1043 
1044     /* Clear interrupt status */
1045     out_be32(&dbell->dbell_regs->dsr, 0x00000091);
1046 
1047     /* Hook up doorbell handler */
1048     rc = request_irq(IRQ_RIO_BELL(dbell), fsl_rio_dbell_handler, 0,
1049              "dbell_rx", (void *)dbell);
1050     if (rc < 0) {
1051         dma_free_coherent(dbell->dev, 512 * DOORBELL_MESSAGE_SIZE,
1052              dbell->dbell_ring.virt, dbell->dbell_ring.phys);
1053         printk(KERN_ERR
1054             "MPC85xx RIO: unable to request inbound doorbell irq");
1055         goto out;
1056     }
1057 
1058     /* Configure doorbells for snooping, 512 entries, and enable */
1059     out_be32(&dbell->dbell_regs->dmr, 0x00108161);
1060 
1061 out:
1062     return rc;
1063 }
1064 
1065 int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node)
1066 {
1067     struct rio_priv *priv;
1068     struct fsl_rmu *rmu;
1069     u64 msg_start;
1070     const u32 *msg_addr;
1071     int mlen;
1072     int aw;
1073 
1074     if (!mport || !mport->priv)
1075         return -EINVAL;
1076 
1077     priv = mport->priv;
1078 
1079     if (!node) {
1080         dev_warn(priv->dev, "Can't get %pOF property 'fsl,rmu'\n",
1081             priv->dev->of_node);
1082         return -EINVAL;
1083     }
1084 
1085     rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL);
1086     if (!rmu)
1087         return -ENOMEM;
1088 
1089     aw = of_n_addr_cells(node);
1090     msg_addr = of_get_property(node, "reg", &mlen);
1091     if (!msg_addr) {
1092         pr_err("%pOF: unable to find 'reg' property of message-unit\n",
1093             node);
1094         kfree(rmu);
1095         return -ENOMEM;
1096     }
1097     msg_start = of_read_number(msg_addr, aw);
1098 
1099     rmu->msg_regs = (struct rio_msg_regs *)
1100             (rmu_regs_win + (u32)msg_start);
1101 
1102     rmu->txirq = irq_of_parse_and_map(node, 0);
1103     rmu->rxirq = irq_of_parse_and_map(node, 1);
1104     printk(KERN_INFO "%pOF: txirq: %d, rxirq %d\n",
1105         node, rmu->txirq, rmu->rxirq);
1106 
1107     priv->rmm_handle = rmu;
1108 
1109     rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1110     rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1111     rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1112 
1113     return 0;
1114 }
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