Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale MPC85xx/MPC86xx RapidIO support
0004  *
0005  * Copyright 2009 Sysgo AG
0006  * Thomas Moll <thomas.moll@sysgo.com>
0007  * - fixed maintenance access routines, check for aligned access
0008  *
0009  * Copyright 2009 Integrated Device Technology, Inc.
0010  * Alex Bounine <alexandre.bounine@idt.com>
0011  * - Added Port-Write message handling
0012  * - Added Machine Check exception handling
0013  *
0014  * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
0015  * Zhang Wei <wei.zhang@freescale.com>
0016  *
0017  * Copyright 2005 MontaVista Software, Inc.
0018  * Matt Porter <mporter@kernel.crashing.org>
0019  */
0020 
0021 #include <linux/init.h>
0022 #include <linux/extable.h>
0023 #include <linux/types.h>
0024 #include <linux/dma-mapping.h>
0025 #include <linux/interrupt.h>
0026 #include <linux/device.h>
0027 #include <linux/of_address.h>
0028 #include <linux/of_irq.h>
0029 #include <linux/of_platform.h>
0030 #include <linux/delay.h>
0031 #include <linux/slab.h>
0032 
0033 #include <linux/io.h>
0034 #include <linux/uaccess.h>
0035 #include <asm/machdep.h>
0036 
0037 #include "fsl_rio.h"
0038 
0039 #undef DEBUG_PW /* Port-Write debugging */
0040 
0041 #define RIO_PORT1_EDCSR     0x0640
0042 #define RIO_PORT2_EDCSR     0x0680
0043 #define RIO_PORT1_IECSR     0x10130
0044 #define RIO_PORT2_IECSR     0x101B0
0045 
0046 #define RIO_GCCSR       0x13c
0047 #define RIO_ESCSR       0x158
0048 #define ESCSR_CLEAR     0x07120204
0049 #define RIO_PORT2_ESCSR     0x178
0050 #define RIO_CCSR        0x15c
0051 #define RIO_LTLEDCSR_IER    0x80000000
0052 #define RIO_LTLEDCSR_PRT    0x01000000
0053 #define IECSR_CLEAR     0x80000000
0054 #define RIO_ISR_AACR        0x10120
0055 #define RIO_ISR_AACR_AA     0x1 /* Accept All ID */
0056 
0057 #define RIWTAR_TRAD_VAL_SHIFT   12
0058 #define RIWTAR_TRAD_MASK    0x00FFFFFF
0059 #define RIWBAR_BADD_VAL_SHIFT   12
0060 #define RIWBAR_BADD_MASK    0x003FFFFF
0061 #define RIWAR_ENABLE        0x80000000
0062 #define RIWAR_TGINT_LOCAL   0x00F00000
0063 #define RIWAR_RDTYP_NO_SNOOP    0x00040000
0064 #define RIWAR_RDTYP_SNOOP   0x00050000
0065 #define RIWAR_WRTYP_NO_SNOOP    0x00004000
0066 #define RIWAR_WRTYP_SNOOP   0x00005000
0067 #define RIWAR_WRTYP_ALLOC   0x00006000
0068 #define RIWAR_SIZE_MASK     0x0000003F
0069 
0070 static DEFINE_SPINLOCK(fsl_rio_config_lock);
0071 
0072 #define ___fsl_read_rio_config(x, addr, err, op, barrier)   \
0073     __asm__ __volatile__(               \
0074         "1: "op" %1,0(%2)\n"        \
0075         "   "barrier"\n"            \
0076         "2:\n"                  \
0077         ".section .fixup,\"ax\"\n"      \
0078         "3: li %1,-1\n"         \
0079         "   li %0,%3\n"         \
0080         "   b 2b\n"             \
0081         ".previous\n"               \
0082         EX_TABLE(1b, 3b)            \
0083         : "=r" (err), "=r" (x)          \
0084         : "b" (addr), "i" (-EFAULT), "0" (err))
0085 
0086 #ifdef CONFIG_BOOKE
0087 #define __fsl_read_rio_config(x, addr, err, op) \
0088     ___fsl_read_rio_config(x, addr, err, op, "mbar")
0089 #else
0090 #define __fsl_read_rio_config(x, addr, err, op) \
0091     ___fsl_read_rio_config(x, addr, err, op, "eieio")
0092 #endif
0093 
0094 void __iomem *rio_regs_win;
0095 void __iomem *rmu_regs_win;
0096 resource_size_t rio_law_start;
0097 
0098 struct fsl_rio_dbell *dbell;
0099 struct fsl_rio_pw *pw;
0100 
0101 #ifdef CONFIG_E500
0102 int fsl_rio_mcheck_exception(struct pt_regs *regs)
0103 {
0104     const struct exception_table_entry *entry;
0105     unsigned long reason;
0106 
0107     if (!rio_regs_win)
0108         return 0;
0109 
0110     reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
0111     if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
0112         /* Check if we are prepared to handle this fault */
0113         entry = search_exception_tables(regs->nip);
0114         if (entry) {
0115             pr_debug("RIO: %s - MC Exception handled\n",
0116                  __func__);
0117             out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
0118                  0);
0119             regs_set_recoverable(regs);
0120             regs_set_return_ip(regs, extable_fixup(entry));
0121             return 1;
0122         }
0123     }
0124 
0125     return 0;
0126 }
0127 EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
0128 #endif
0129 
0130 /**
0131  * fsl_local_config_read - Generate a MPC85xx local config space read
0132  * @mport: RapidIO master port info
0133  * @index: ID of RapdiIO interface
0134  * @offset: Offset into configuration space
0135  * @len: Length (in bytes) of the maintenance transaction
0136  * @data: Value to be read into
0137  *
0138  * Generates a MPC85xx local configuration space read. Returns %0 on
0139  * success or %-EINVAL on failure.
0140  */
0141 static int fsl_local_config_read(struct rio_mport *mport,
0142                 int index, u32 offset, int len, u32 *data)
0143 {
0144     struct rio_priv *priv = mport->priv;
0145     pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
0146          offset);
0147     *data = in_be32(priv->regs_win + offset);
0148 
0149     return 0;
0150 }
0151 
0152 /**
0153  * fsl_local_config_write - Generate a MPC85xx local config space write
0154  * @mport: RapidIO master port info
0155  * @index: ID of RapdiIO interface
0156  * @offset: Offset into configuration space
0157  * @len: Length (in bytes) of the maintenance transaction
0158  * @data: Value to be written
0159  *
0160  * Generates a MPC85xx local configuration space write. Returns %0 on
0161  * success or %-EINVAL on failure.
0162  */
0163 static int fsl_local_config_write(struct rio_mport *mport,
0164                 int index, u32 offset, int len, u32 data)
0165 {
0166     struct rio_priv *priv = mport->priv;
0167     pr_debug
0168         ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
0169         index, offset, data);
0170     out_be32(priv->regs_win + offset, data);
0171 
0172     return 0;
0173 }
0174 
0175 /**
0176  * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
0177  * @mport: RapidIO master port info
0178  * @index: ID of RapdiIO interface
0179  * @destid: Destination ID of transaction
0180  * @hopcount: Number of hops to target device
0181  * @offset: Offset into configuration space
0182  * @len: Length (in bytes) of the maintenance transaction
0183  * @val: Location to be read into
0184  *
0185  * Generates a MPC85xx read maintenance transaction. Returns %0 on
0186  * success or %-EINVAL on failure.
0187  */
0188 static int
0189 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
0190             u8 hopcount, u32 offset, int len, u32 *val)
0191 {
0192     struct rio_priv *priv = mport->priv;
0193     unsigned long flags;
0194     u8 *data;
0195     u32 rval, err = 0;
0196 
0197     pr_debug
0198         ("fsl_rio_config_read:"
0199         " index %d destid %d hopcount %d offset %8.8x len %d\n",
0200         index, destid, hopcount, offset, len);
0201 
0202     /* 16MB maintenance window possible */
0203     /* allow only aligned access to maintenance registers */
0204     if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
0205         return -EINVAL;
0206 
0207     spin_lock_irqsave(&fsl_rio_config_lock, flags);
0208 
0209     out_be32(&priv->maint_atmu_regs->rowtar,
0210          (destid << 22) | (hopcount << 12) | (offset >> 12));
0211     out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
0212 
0213     data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
0214     switch (len) {
0215     case 1:
0216         __fsl_read_rio_config(rval, data, err, "lbz");
0217         break;
0218     case 2:
0219         __fsl_read_rio_config(rval, data, err, "lhz");
0220         break;
0221     case 4:
0222         __fsl_read_rio_config(rval, data, err, "lwz");
0223         break;
0224     default:
0225         spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
0226         return -EINVAL;
0227     }
0228 
0229     if (err) {
0230         pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
0231              err, destid, hopcount, offset);
0232     }
0233 
0234     spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
0235     *val = rval;
0236 
0237     return err;
0238 }
0239 
0240 /**
0241  * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
0242  * @mport: RapidIO master port info
0243  * @index: ID of RapdiIO interface
0244  * @destid: Destination ID of transaction
0245  * @hopcount: Number of hops to target device
0246  * @offset: Offset into configuration space
0247  * @len: Length (in bytes) of the maintenance transaction
0248  * @val: Value to be written
0249  *
0250  * Generates an MPC85xx write maintenance transaction. Returns %0 on
0251  * success or %-EINVAL on failure.
0252  */
0253 static int
0254 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
0255             u8 hopcount, u32 offset, int len, u32 val)
0256 {
0257     struct rio_priv *priv = mport->priv;
0258     unsigned long flags;
0259     u8 *data;
0260     int ret = 0;
0261 
0262     pr_debug
0263         ("fsl_rio_config_write:"
0264         " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
0265         index, destid, hopcount, offset, len, val);
0266 
0267     /* 16MB maintenance windows possible */
0268     /* allow only aligned access to maintenance registers */
0269     if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
0270         return -EINVAL;
0271 
0272     spin_lock_irqsave(&fsl_rio_config_lock, flags);
0273 
0274     out_be32(&priv->maint_atmu_regs->rowtar,
0275          (destid << 22) | (hopcount << 12) | (offset >> 12));
0276     out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
0277 
0278     data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
0279     switch (len) {
0280     case 1:
0281         out_8((u8 *) data, val);
0282         break;
0283     case 2:
0284         out_be16((u16 *) data, val);
0285         break;
0286     case 4:
0287         out_be32((u32 *) data, val);
0288         break;
0289     default:
0290         ret = -EINVAL;
0291     }
0292     spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
0293 
0294     return ret;
0295 }
0296 
0297 static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
0298 {
0299     int i;
0300 
0301     /* close inbound windows */
0302     for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
0303         out_be32(&priv->inb_atmu_regs[i].riwar, 0);
0304 }
0305 
0306 int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
0307     u64 rstart, u64 size, u32 flags)
0308 {
0309     struct rio_priv *priv = mport->priv;
0310     u32 base_size;
0311     unsigned int base_size_log;
0312     u64 win_start, win_end;
0313     u32 riwar;
0314     int i;
0315 
0316     if ((size & (size - 1)) != 0 || size > 0x400000000ULL)
0317         return -EINVAL;
0318 
0319     base_size_log = ilog2(size);
0320     base_size = 1 << base_size_log;
0321 
0322     /* check if addresses are aligned with the window size */
0323     if (lstart & (base_size - 1))
0324         return -EINVAL;
0325     if (rstart & (base_size - 1))
0326         return -EINVAL;
0327 
0328     /* check for conflicting ranges */
0329     for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
0330         riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
0331         if ((riwar & RIWAR_ENABLE) == 0)
0332             continue;
0333         win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
0334             << RIWBAR_BADD_VAL_SHIFT;
0335         win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
0336         if (rstart < win_end && (rstart + size) > win_start)
0337             return -EINVAL;
0338     }
0339 
0340     /* find unused atmu */
0341     for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
0342         riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
0343         if ((riwar & RIWAR_ENABLE) == 0)
0344             break;
0345     }
0346     if (i >= RIO_INB_ATMU_COUNT)
0347         return -ENOMEM;
0348 
0349     out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
0350     out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
0351     out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
0352         RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
0353 
0354     return 0;
0355 }
0356 
0357 void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
0358 {
0359     u32 win_start_shift, base_start_shift;
0360     struct rio_priv *priv = mport->priv;
0361     u32 riwar, riwtar;
0362     int i;
0363 
0364     /* skip default window */
0365     base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
0366     for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
0367         riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
0368         if ((riwar & RIWAR_ENABLE) == 0)
0369             continue;
0370 
0371         riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
0372         win_start_shift = riwtar & RIWTAR_TRAD_MASK;
0373         if (win_start_shift == base_start_shift) {
0374             out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
0375             return;
0376         }
0377     }
0378 }
0379 
0380 void fsl_rio_port_error_handler(int offset)
0381 {
0382     /*XXX: Error recovery is not implemented, we just clear errors */
0383     out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
0384 
0385     if (offset == 0) {
0386         out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
0387         out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
0388         out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
0389     } else {
0390         out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
0391         out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
0392         out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
0393     }
0394 }
0395 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
0396 {
0397     const char *str;
0398     if (ccsr & 1) {
0399         /* Serial phy */
0400         switch (ccsr >> 30) {
0401         case 0:
0402             str = "1";
0403             break;
0404         case 1:
0405             str = "4";
0406             break;
0407         default:
0408             str = "Unknown";
0409             break;
0410         }
0411         dev_info(dev, "Hardware port width: %s\n", str);
0412 
0413         switch ((ccsr >> 27) & 7) {
0414         case 0:
0415             str = "Single-lane 0";
0416             break;
0417         case 1:
0418             str = "Single-lane 2";
0419             break;
0420         case 2:
0421             str = "Four-lane";
0422             break;
0423         default:
0424             str = "Unknown";
0425             break;
0426         }
0427         dev_info(dev, "Training connection status: %s\n", str);
0428     } else {
0429         /* Parallel phy */
0430         if (!(ccsr & 0x80000000))
0431             dev_info(dev, "Output port operating in 8-bit mode\n");
0432         if (!(ccsr & 0x08000000))
0433             dev_info(dev, "Input port operating in 8-bit mode\n");
0434     }
0435 }
0436 
0437 /**
0438  * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
0439  * @dev: platform_device pointer
0440  *
0441  * Initializes MPC85xx RapidIO hardware interface, configures
0442  * master port with system-specific info, and registers the
0443  * master port with the RapidIO subsystem.
0444  */
0445 int fsl_rio_setup(struct platform_device *dev)
0446 {
0447     struct rio_ops *ops;
0448     struct rio_mport *port;
0449     struct rio_priv *priv;
0450     int rc = 0;
0451     const u32 *dt_range, *cell, *port_index;
0452     u32 active_ports = 0;
0453     struct resource regs, rmu_regs;
0454     struct device_node *np, *rmu_node;
0455     int rlen;
0456     u32 ccsr;
0457     u64 range_start, range_size;
0458     int paw, aw, sw;
0459     u32 i;
0460     static int tmp;
0461     struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
0462 
0463     if (!dev->dev.of_node) {
0464         dev_err(&dev->dev, "Device OF-Node is NULL");
0465         return -ENODEV;
0466     }
0467 
0468     rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
0469     if (rc) {
0470         dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
0471                 dev->dev.of_node);
0472         return -EFAULT;
0473     }
0474     dev_info(&dev->dev, "Of-device full name %pOF\n",
0475             dev->dev.of_node);
0476     dev_info(&dev->dev, "Regs: %pR\n", &regs);
0477 
0478     rio_regs_win = ioremap(regs.start, resource_size(&regs));
0479     if (!rio_regs_win) {
0480         dev_err(&dev->dev, "Unable to map rio register window\n");
0481         rc = -ENOMEM;
0482         goto err_rio_regs;
0483     }
0484 
0485     ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
0486     if (!ops) {
0487         rc = -ENOMEM;
0488         goto err_ops;
0489     }
0490     ops->lcread = fsl_local_config_read;
0491     ops->lcwrite = fsl_local_config_write;
0492     ops->cread = fsl_rio_config_read;
0493     ops->cwrite = fsl_rio_config_write;
0494     ops->dsend = fsl_rio_doorbell_send;
0495     ops->pwenable = fsl_rio_pw_enable;
0496     ops->open_outb_mbox = fsl_open_outb_mbox;
0497     ops->open_inb_mbox = fsl_open_inb_mbox;
0498     ops->close_outb_mbox = fsl_close_outb_mbox;
0499     ops->close_inb_mbox = fsl_close_inb_mbox;
0500     ops->add_outb_message = fsl_add_outb_message;
0501     ops->add_inb_buffer = fsl_add_inb_buffer;
0502     ops->get_inb_message = fsl_get_inb_message;
0503     ops->map_inb = fsl_map_inb_mem;
0504     ops->unmap_inb = fsl_unmap_inb_mem;
0505 
0506     rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
0507     if (!rmu_node) {
0508         dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
0509         rc = -ENOENT;
0510         goto err_rmu;
0511     }
0512     rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
0513     if (rc) {
0514         dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
0515                 rmu_node);
0516         of_node_put(rmu_node);
0517         goto err_rmu;
0518     }
0519     of_node_put(rmu_node);
0520     rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
0521     if (!rmu_regs_win) {
0522         dev_err(&dev->dev, "Unable to map rmu register window\n");
0523         rc = -ENOMEM;
0524         goto err_rmu;
0525     }
0526     for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
0527         rmu_np[tmp] = np;
0528         tmp++;
0529     }
0530 
0531     /*set up doobell node*/
0532     np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
0533     if (!np) {
0534         dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
0535         rc = -ENODEV;
0536         goto err_dbell;
0537     }
0538     dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
0539     if (!(dbell)) {
0540         dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
0541         rc = -ENOMEM;
0542         goto err_dbell;
0543     }
0544     dbell->dev = &dev->dev;
0545     dbell->bellirq = irq_of_parse_and_map(np, 1);
0546     dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
0547 
0548     aw = of_n_addr_cells(np);
0549     dt_range = of_get_property(np, "reg", &rlen);
0550     if (!dt_range) {
0551         pr_err("%pOF: unable to find 'reg' property\n",
0552             np);
0553         rc = -ENOMEM;
0554         goto err_pw;
0555     }
0556     range_start = of_read_number(dt_range, aw);
0557     dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
0558                 (u32)range_start);
0559 
0560     /*set up port write node*/
0561     np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
0562     if (!np) {
0563         dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
0564         rc = -ENODEV;
0565         goto err_pw;
0566     }
0567     pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
0568     if (!(pw)) {
0569         dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
0570         rc = -ENOMEM;
0571         goto err_pw;
0572     }
0573     pw->dev = &dev->dev;
0574     pw->pwirq = irq_of_parse_and_map(np, 0);
0575     dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
0576     aw = of_n_addr_cells(np);
0577     dt_range = of_get_property(np, "reg", &rlen);
0578     if (!dt_range) {
0579         pr_err("%pOF: unable to find 'reg' property\n",
0580             np);
0581         rc = -ENOMEM;
0582         goto err;
0583     }
0584     range_start = of_read_number(dt_range, aw);
0585     pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
0586 
0587     /*set up ports node*/
0588     for_each_child_of_node(dev->dev.of_node, np) {
0589         port_index = of_get_property(np, "cell-index", NULL);
0590         if (!port_index) {
0591             dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n",
0592                     np);
0593             continue;
0594         }
0595 
0596         dt_range = of_get_property(np, "ranges", &rlen);
0597         if (!dt_range) {
0598             dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n",
0599                     np);
0600             continue;
0601         }
0602 
0603         /* Get node address wide */
0604         cell = of_get_property(np, "#address-cells", NULL);
0605         if (cell)
0606             aw = *cell;
0607         else
0608             aw = of_n_addr_cells(np);
0609         /* Get node size wide */
0610         cell = of_get_property(np, "#size-cells", NULL);
0611         if (cell)
0612             sw = *cell;
0613         else
0614             sw = of_n_size_cells(np);
0615         /* Get parent address wide wide */
0616         paw = of_n_addr_cells(np);
0617         range_start = of_read_number(dt_range + aw, paw);
0618         range_size = of_read_number(dt_range + aw + paw, sw);
0619 
0620         dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n",
0621                 np, range_start, range_size);
0622 
0623         port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
0624         if (!port)
0625             continue;
0626 
0627         rc = rio_mport_initialize(port);
0628         if (rc) {
0629             kfree(port);
0630             continue;
0631         }
0632 
0633         i = *port_index - 1;
0634         port->index = (unsigned char)i;
0635 
0636         priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
0637         if (!priv) {
0638             dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
0639             kfree(port);
0640             continue;
0641         }
0642 
0643         INIT_LIST_HEAD(&port->dbells);
0644         port->iores.start = range_start;
0645         port->iores.end = port->iores.start + range_size - 1;
0646         port->iores.flags = IORESOURCE_MEM;
0647         port->iores.name = "rio_io_win";
0648 
0649         if (request_resource(&iomem_resource, &port->iores) < 0) {
0650             dev_err(&dev->dev, "RIO: Error requesting master port region"
0651                 " 0x%016llx-0x%016llx\n",
0652                 (u64)port->iores.start, (u64)port->iores.end);
0653                 kfree(priv);
0654                 kfree(port);
0655                 continue;
0656         }
0657         sprintf(port->name, "RIO mport %d", i);
0658 
0659         priv->dev = &dev->dev;
0660         port->dev.parent = &dev->dev;
0661         port->ops = ops;
0662         port->priv = priv;
0663         port->phys_efptr = 0x100;
0664         port->phys_rmap = 1;
0665         priv->regs_win = rio_regs_win;
0666 
0667         ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
0668 
0669         /* Checking the port training status */
0670         if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
0671             dev_err(&dev->dev, "Port %d is not ready. "
0672             "Try to restart connection...\n", i);
0673             /* Disable ports */
0674             out_be32(priv->regs_win
0675                 + RIO_CCSR + i*0x20, 0);
0676             /* Set 1x lane */
0677             setbits32(priv->regs_win
0678                 + RIO_CCSR + i*0x20, 0x02000000);
0679             /* Enable ports */
0680             setbits32(priv->regs_win
0681                 + RIO_CCSR + i*0x20, 0x00600000);
0682             msleep(100);
0683             if (in_be32((priv->regs_win
0684                     + RIO_ESCSR + i*0x20)) & 1) {
0685                 dev_err(&dev->dev,
0686                     "Port %d restart failed.\n", i);
0687                 release_resource(&port->iores);
0688                 kfree(priv);
0689                 kfree(port);
0690                 continue;
0691             }
0692             dev_info(&dev->dev, "Port %d restart success!\n", i);
0693         }
0694         fsl_rio_info(&dev->dev, ccsr);
0695 
0696         port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
0697                     & RIO_PEF_CTLS) >> 4;
0698         dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
0699                 port->sys_size ? 65536 : 256);
0700 
0701         if (port->host_deviceid >= 0)
0702             out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
0703                 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
0704         else
0705             out_be32(priv->regs_win + RIO_GCCSR,
0706                 RIO_PORT_GEN_MASTER);
0707 
0708         priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
0709             + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
0710             RIO_ATMU_REGS_PORT2_OFFSET));
0711 
0712         priv->maint_atmu_regs = priv->atmu_regs + 1;
0713         priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
0714             (priv->regs_win +
0715             ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
0716             RIO_INB_ATMU_REGS_PORT2_OFFSET));
0717 
0718         /* Set to receive packets with any dest ID */
0719         out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),
0720              RIO_ISR_AACR_AA);
0721 
0722         /* Configure maintenance transaction window */
0723         out_be32(&priv->maint_atmu_regs->rowbar,
0724             port->iores.start >> 12);
0725         out_be32(&priv->maint_atmu_regs->rowar,
0726              0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
0727 
0728         priv->maint_win = ioremap(port->iores.start,
0729                 RIO_MAINT_WIN_SIZE);
0730 
0731         rio_law_start = range_start;
0732 
0733         fsl_rio_setup_rmu(port, rmu_np[i]);
0734         fsl_rio_inbound_mem_init(priv);
0735 
0736         dbell->mport[i] = port;
0737         pw->mport[i] = port;
0738 
0739         if (rio_register_mport(port)) {
0740             release_resource(&port->iores);
0741             kfree(priv);
0742             kfree(port);
0743             continue;
0744         }
0745         active_ports++;
0746     }
0747 
0748     if (!active_ports) {
0749         rc = -ENOLINK;
0750         goto err;
0751     }
0752 
0753     fsl_rio_doorbell_init(dbell);
0754     fsl_rio_port_write_init(pw);
0755 
0756     return 0;
0757 err:
0758     kfree(pw);
0759     pw = NULL;
0760 err_pw:
0761     kfree(dbell);
0762     dbell = NULL;
0763 err_dbell:
0764     iounmap(rmu_regs_win);
0765     rmu_regs_win = NULL;
0766 err_rmu:
0767     kfree(ops);
0768 err_ops:
0769     iounmap(rio_regs_win);
0770     rio_regs_win = NULL;
0771 err_rio_regs:
0772     return rc;
0773 }
0774 
0775 /* The probe function for RapidIO peer-to-peer network.
0776  */
0777 static int fsl_of_rio_rpn_probe(struct platform_device *dev)
0778 {
0779     printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n",
0780             dev->dev.of_node);
0781 
0782     return fsl_rio_setup(dev);
0783 };
0784 
0785 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
0786     {
0787         .compatible = "fsl,srio",
0788     },
0789     {},
0790 };
0791 
0792 static struct platform_driver fsl_of_rio_rpn_driver = {
0793     .driver = {
0794         .name = "fsl-of-rio",
0795         .of_match_table = fsl_of_rio_rpn_ids,
0796     },
0797     .probe = fsl_of_rio_rpn_probe,
0798 };
0799 
0800 static __init int fsl_of_rio_rpn_init(void)
0801 {
0802     return platform_driver_register(&fsl_of_rio_rpn_driver);
0803 }
0804 
0805 subsys_initcall(fsl_of_rio_rpn_init);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!