powerpc/sysdev/fsl_rcpm.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * RCPM(Run Control/Power Management) support
0004  *
0005  * Copyright 2012-2015 Freescale Semiconductor Inc.
0006  *
0007  * Author: Chenhui Zhao <chenhui.zhao@freescale.com>
0008  */
0009
0010 #define pr_fmt(fmt) "%s: " fmt, __func__
0011
0012 #include <linux/types.h>
0013 #include <linux/errno.h>
0014 #include <linux/of_address.h>
0015 #include <linux/export.h>
0016
0017 #include <asm/io.h>
0018 #include <linux/fsl/guts.h>
0019 #include <asm/cputhreads.h>
0020 #include <asm/fsl_pm.h>
0021 #include <asm/smp.h>
0022
0023 static struct ccsr_rcpm_v1 __iomem *rcpm_v1_regs;
0024 static struct ccsr_rcpm_v2 __iomem *rcpm_v2_regs;
0025 static unsigned int fsl_supported_pm_modes;
0026
0027 static void rcpm_v1_irq_mask(int cpu)
0028 {
0029     int hw_cpu = get_hard_smp_processor_id(cpu);
0030     unsigned int mask = 1 << hw_cpu;
0031
0032     setbits32(&rcpm_v1_regs->cpmimr, mask);
0033     setbits32(&rcpm_v1_regs->cpmcimr, mask);
0034     setbits32(&rcpm_v1_regs->cpmmcmr, mask);
0035     setbits32(&rcpm_v1_regs->cpmnmimr, mask);
0036 }
0037
0038 static void rcpm_v2_irq_mask(int cpu)
0039 {
0040     int hw_cpu = get_hard_smp_processor_id(cpu);
0041     unsigned int mask = 1 << hw_cpu;
0042
0043     setbits32(&rcpm_v2_regs->tpmimr0, mask);
0044     setbits32(&rcpm_v2_regs->tpmcimr0, mask);
0045     setbits32(&rcpm_v2_regs->tpmmcmr0, mask);
0046     setbits32(&rcpm_v2_regs->tpmnmimr0, mask);
0047 }
0048
0049 static void rcpm_v1_irq_unmask(int cpu)
0050 {
0051     int hw_cpu = get_hard_smp_processor_id(cpu);
0052     unsigned int mask = 1 << hw_cpu;
0053
0054     clrbits32(&rcpm_v1_regs->cpmimr, mask);
0055     clrbits32(&rcpm_v1_regs->cpmcimr, mask);
0056     clrbits32(&rcpm_v1_regs->cpmmcmr, mask);
0057     clrbits32(&rcpm_v1_regs->cpmnmimr, mask);
0058 }
0059
0060 static void rcpm_v2_irq_unmask(int cpu)
0061 {
0062     int hw_cpu = get_hard_smp_processor_id(cpu);
0063     unsigned int mask = 1 << hw_cpu;
0064
0065     clrbits32(&rcpm_v2_regs->tpmimr0, mask);
0066     clrbits32(&rcpm_v2_regs->tpmcimr0, mask);
0067     clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);
0068     clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);
0069 }
0070
0071 static void rcpm_v1_set_ip_power(bool enable, u32 mask)
0072 {
0073     if (enable)
0074         setbits32(&rcpm_v1_regs->ippdexpcr, mask);
0075     else
0076         clrbits32(&rcpm_v1_regs->ippdexpcr, mask);
0077 }
0078
0079 static void rcpm_v2_set_ip_power(bool enable, u32 mask)
0080 {
0081     if (enable)
0082         setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
0083     else
0084         clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
0085 }
0086
0087 static void rcpm_v1_cpu_enter_state(int cpu, int state)
0088 {
0089     int hw_cpu = get_hard_smp_processor_id(cpu);
0090     unsigned int mask = 1 << hw_cpu;
0091
0092     switch (state) {
0093     case E500_PM_PH10:
0094         setbits32(&rcpm_v1_regs->cdozcr, mask);
0095         break;
0096     case E500_PM_PH15:
0097         setbits32(&rcpm_v1_regs->cnapcr, mask);
0098         break;
0099     default:
0100         pr_warn("Unknown cpu PM state (%d)\n", state);
0101         break;
0102     }
0103 }
0104
0105 static void rcpm_v2_cpu_enter_state(int cpu, int state)
0106 {
0107     int hw_cpu = get_hard_smp_processor_id(cpu);
0108     u32 mask = 1 << cpu_core_index_of_thread(cpu);
0109
0110     switch (state) {
0111     case E500_PM_PH10:
0112         /* one bit corresponds to one thread for PH10 of 6500 */
0113         setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);
0114         break;
0115     case E500_PM_PH15:
0116         setbits32(&rcpm_v2_regs->pcph15setr, mask);
0117         break;
0118     case E500_PM_PH20:
0119         setbits32(&rcpm_v2_regs->pcph20setr, mask);
0120         break;
0121     case E500_PM_PH30:
0122         setbits32(&rcpm_v2_regs->pcph30setr, mask);
0123         break;
0124     default:
0125         pr_warn("Unknown cpu PM state (%d)\n", state);
0126     }
0127 }
0128
0129 static void rcpm_v1_cpu_die(int cpu)
0130 {
0131     rcpm_v1_cpu_enter_state(cpu, E500_PM_PH15);
0132 }
0133
0134 #ifdef CONFIG_PPC64
0135 static void qoriq_disable_thread(int cpu)
0136 {
0137     int thread = cpu_thread_in_core(cpu);
0138
0139     book3e_stop_thread(thread);
0140 }
0141 #endif
0142
0143 static void rcpm_v2_cpu_die(int cpu)
0144 {
0145 #ifdef CONFIG_PPC64
0146     int primary;
0147
0148     if (threads_per_core == 2) {
0149         primary = cpu_first_thread_sibling(cpu);
0150         if (cpu_is_offline(primary) && cpu_is_offline(primary + 1)) {
0151             /* if both threads are offline, put the cpu in PH20 */
0152             rcpm_v2_cpu_enter_state(cpu, E500_PM_PH20);
0153         } else {
0154             /* if only one thread is offline, disable the thread */
0155             qoriq_disable_thread(cpu);
0156         }
0157     }
0158 #endif
0159
0160     if (threads_per_core == 1)
0161         rcpm_v2_cpu_enter_state(cpu, E500_PM_PH20);
0162 }
0163
0164 static void rcpm_v1_cpu_exit_state(int cpu, int state)
0165 {
0166     int hw_cpu = get_hard_smp_processor_id(cpu);
0167     unsigned int mask = 1 << hw_cpu;
0168
0169     switch (state) {
0170     case E500_PM_PH10:
0171         clrbits32(&rcpm_v1_regs->cdozcr, mask);
0172         break;
0173     case E500_PM_PH15:
0174         clrbits32(&rcpm_v1_regs->cnapcr, mask);
0175         break;
0176     default:
0177         pr_warn("Unknown cpu PM state (%d)\n", state);
0178         break;
0179     }
0180 }
0181
0182 static void rcpm_v1_cpu_up_prepare(int cpu)
0183 {
0184     rcpm_v1_cpu_exit_state(cpu, E500_PM_PH15);
0185     rcpm_v1_irq_unmask(cpu);
0186 }
0187
0188 static void rcpm_v2_cpu_exit_state(int cpu, int state)
0189 {
0190     int hw_cpu = get_hard_smp_processor_id(cpu);
0191     u32 mask = 1 << cpu_core_index_of_thread(cpu);
0192
0193     switch (state) {
0194     case E500_PM_PH10:
0195         setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);
0196         break;
0197     case E500_PM_PH15:
0198         setbits32(&rcpm_v2_regs->pcph15clrr, mask);
0199         break;
0200     case E500_PM_PH20:
0201         setbits32(&rcpm_v2_regs->pcph20clrr, mask);
0202         break;
0203     case E500_PM_PH30:
0204         setbits32(&rcpm_v2_regs->pcph30clrr, mask);
0205         break;
0206     default:
0207         pr_warn("Unknown cpu PM state (%d)\n", state);
0208     }
0209 }
0210
0211 static void rcpm_v2_cpu_up_prepare(int cpu)
0212 {
0213     rcpm_v2_cpu_exit_state(cpu, E500_PM_PH20);
0214     rcpm_v2_irq_unmask(cpu);
0215 }
0216
0217 static int rcpm_v1_plat_enter_state(int state)
0218 {
0219     u32 *pmcsr_reg = &rcpm_v1_regs->powmgtcsr;
0220     int ret = 0;
0221     int result;
0222
0223     switch (state) {
0224     case PLAT_PM_SLEEP:
0225         setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP);
0226
0227         /* Upon resume, wait for RCPM_POWMGTCSR_SLP bit to be clear. */
0228         result = spin_event_timeout(
0229           !(in_be32(pmcsr_reg) & RCPM_POWMGTCSR_SLP), 10000, 10);
0230         if (!result) {
0231             pr_err("timeout waiting for SLP bit to be cleared\n");
0232             ret = -ETIMEDOUT;
0233         }
0234         break;
0235     default:
0236         pr_warn("Unknown platform PM state (%d)", state);
0237         ret = -EINVAL;
0238     }
0239
0240     return ret;
0241 }
0242
0243 static int rcpm_v2_plat_enter_state(int state)
0244 {
0245     u32 *pmcsr_reg = &rcpm_v2_regs->powmgtcsr;
0246     int ret = 0;
0247     int result;
0248
0249     switch (state) {
0250     case PLAT_PM_LPM20:
0251         /* clear previous LPM20 status */
0252         setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);
0253         /* enter LPM20 status */
0254         setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);
0255
0256         /* At this point, the device is in LPM20 status. */
0257
0258         /* resume ... */
0259         result = spin_event_timeout(
0260           !(in_be32(pmcsr_reg) & RCPM_POWMGTCSR_LPM20_ST), 10000, 10);
0261         if (!result) {
0262             pr_err("timeout waiting for LPM20 bit to be cleared\n");
0263             ret = -ETIMEDOUT;
0264         }
0265         break;
0266     default:
0267         pr_warn("Unknown platform PM state (%d)\n", state);
0268         ret = -EINVAL;
0269     }
0270
0271     return ret;
0272 }
0273
0274 static int rcpm_v1_plat_enter_sleep(void)
0275 {
0276     return rcpm_v1_plat_enter_state(PLAT_PM_SLEEP);
0277 }
0278
0279 static int rcpm_v2_plat_enter_sleep(void)
0280 {
0281     return rcpm_v2_plat_enter_state(PLAT_PM_LPM20);
0282 }
0283
0284 static void rcpm_common_freeze_time_base(u32 *tben_reg, int freeze)
0285 {
0286     static u32 mask;
0287
0288     if (freeze) {
0289         mask = in_be32(tben_reg);
0290         clrbits32(tben_reg, mask);
0291     } else {
0292         setbits32(tben_reg, mask);
0293     }
0294
0295     /* read back to push the previous write */
0296     in_be32(tben_reg);
0297 }
0298
0299 static void rcpm_v1_freeze_time_base(bool freeze)
0300 {
0301     rcpm_common_freeze_time_base(&rcpm_v1_regs->ctbenr, freeze);
0302 }
0303
0304 static void rcpm_v2_freeze_time_base(bool freeze)
0305 {
0306     rcpm_common_freeze_time_base(&rcpm_v2_regs->pctbenr, freeze);
0307 }
0308
0309 static unsigned int rcpm_get_pm_modes(void)
0310 {
0311     return fsl_supported_pm_modes;
0312 }
0313
0314 static const struct fsl_pm_ops qoriq_rcpm_v1_ops = {
0315     .irq_mask = rcpm_v1_irq_mask,
0316     .irq_unmask = rcpm_v1_irq_unmask,
0317     .cpu_enter_state = rcpm_v1_cpu_enter_state,
0318     .cpu_exit_state = rcpm_v1_cpu_exit_state,
0319     .cpu_up_prepare = rcpm_v1_cpu_up_prepare,
0320     .cpu_die = rcpm_v1_cpu_die,
0321     .plat_enter_sleep = rcpm_v1_plat_enter_sleep,
0322     .set_ip_power = rcpm_v1_set_ip_power,
0323     .freeze_time_base = rcpm_v1_freeze_time_base,
0324     .get_pm_modes = rcpm_get_pm_modes,
0325 };
0326
0327 static const struct fsl_pm_ops qoriq_rcpm_v2_ops = {
0328     .irq_mask = rcpm_v2_irq_mask,
0329     .irq_unmask = rcpm_v2_irq_unmask,
0330     .cpu_enter_state = rcpm_v2_cpu_enter_state,
0331     .cpu_exit_state = rcpm_v2_cpu_exit_state,
0332     .cpu_up_prepare = rcpm_v2_cpu_up_prepare,
0333     .cpu_die = rcpm_v2_cpu_die,
0334     .plat_enter_sleep = rcpm_v2_plat_enter_sleep,
0335     .set_ip_power = rcpm_v2_set_ip_power,
0336     .freeze_time_base = rcpm_v2_freeze_time_base,
0337     .get_pm_modes = rcpm_get_pm_modes,
0338 };
0339
0340 static const struct of_device_id rcpm_matches[] = {
0341     {
0342         .compatible = "fsl,qoriq-rcpm-1.0",
0343         .data = &qoriq_rcpm_v1_ops,
0344     },
0345     {
0346         .compatible = "fsl,qoriq-rcpm-2.0",
0347         .data = &qoriq_rcpm_v2_ops,
0348     },
0349     {
0350         .compatible = "fsl,qoriq-rcpm-2.1",
0351         .data = &qoriq_rcpm_v2_ops,
0352     },
0353     {},
0354 };
0355
0356 int __init fsl_rcpm_init(void)
0357 {
0358     struct device_node *np;
0359     const struct of_device_id *match;
0360     void __iomem *base;
0361
0362     np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
0363     if (!np)
0364         return 0;
0365
0366     base = of_iomap(np, 0);
0367     of_node_put(np);
0368     if (!base) {
0369         pr_err("of_iomap() error.\n");
0370         return -ENOMEM;
0371     }
0372
0373     rcpm_v1_regs = base;
0374     rcpm_v2_regs = base;
0375
0376     /* support sleep by default */
0377     fsl_supported_pm_modes = FSL_PM_SLEEP;
0378
0379     qoriq_pm_ops = match->data;
0380
0381     return 0;
0382 }