powerpc/sysdev/fsl_pci.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * MPC85xx/86xx PCI Express structure define
0004  *
0005  * Copyright 2007,2011 Freescale Semiconductor, Inc
0006  */
0007
0008 #ifdef __KERNEL__
0009 #ifndef __POWERPC_FSL_PCI_H
0010 #define __POWERPC_FSL_PCI_H
0011
0012 struct platform_device;
0013
0014
0015 /* FSL PCI controller BRR1 register */
0016 #define PCI_FSL_BRR1      0xbf8
0017 #define PCI_FSL_BRR1_VER 0xffff
0018
0019 #define PCIE_LTSSM  0x0404      /* PCIE Link Training and Status */
0020 #define PCIE_LTSSM_L0   0x16        /* L0 state */
0021 #define PCIE_FSL_CSR_CLASSCODE  0x474   /* FSL GPEX CSR */
0022 #define PCIE_IP_REV_2_2     0x02080202 /* PCIE IP block version Rev2.2 */
0023 #define PCIE_IP_REV_3_0     0x02080300 /* PCIE IP block version Rev3.0 */
0024 #define PIWAR_EN        0x80000000  /* Enable */
0025 #define PIWAR_PF        0x20000000  /* prefetch */
0026 #define PIWAR_TGI_LOCAL     0x00f00000  /* target - local memory */
0027 #define PIWAR_READ_SNOOP    0x00050000
0028 #define PIWAR_WRITE_SNOOP   0x00005000
0029 #define PIWAR_SZ_MASK          0x0000003f
0030
0031 #define PEX_PMCR_PTOMR      0x1
0032 #define PEX_PMCR_EXL2S      0x2
0033
0034 #define PME_DISR_EN_PTOD    0x00008000
0035 #define PME_DISR_EN_ENL23D  0x00002000
0036 #define PME_DISR_EN_EXL23D  0x00001000
0037
0038 /* PCI/PCI Express outbound window reg */
0039 struct pci_outbound_window_regs {
0040     __be32  potar;  /* 0x.0 - Outbound translation address register */
0041     __be32  potear; /* 0x.4 - Outbound translation extended address register */
0042     __be32  powbar; /* 0x.8 - Outbound window base address register */
0043     u8  res1[4];
0044     __be32  powar;  /* 0x.10 - Outbound window attributes register */
0045     u8  res2[12];
0046 };
0047
0048 /* PCI/PCI Express inbound window reg */
0049 struct pci_inbound_window_regs {
0050     __be32  pitar;  /* 0x.0 - Inbound translation address register */
0051     u8  res1[4];
0052     __be32  piwbar; /* 0x.8 - Inbound window base address register */
0053     __be32  piwbear;    /* 0x.c - Inbound window base extended address register */
0054     __be32  piwar;  /* 0x.10 - Inbound window attributes register */
0055     u8  res2[12];
0056 };
0057
0058 /* PCI/PCI Express IO block registers for 85xx/86xx */
0059 struct ccsr_pci {
0060     __be32  config_addr;        /* 0x.000 - PCI/PCIE Configuration Address Register */
0061     __be32  config_data;        /* 0x.004 - PCI/PCIE Configuration Data Register */
0062     __be32  int_ack;        /* 0x.008 - PCI Interrupt Acknowledge Register */
0063     __be32  pex_otb_cpl_tor;    /* 0x.00c - PCIE Outbound completion timeout register */
0064     __be32  pex_conf_tor;       /* 0x.010 - PCIE configuration timeout register */
0065     __be32  pex_config;     /* 0x.014 - PCIE CONFIG Register */
0066     __be32  pex_int_status;     /* 0x.018 - PCIE interrupt status */
0067     u8  res2[4];
0068     __be32  pex_pme_mes_dr;     /* 0x.020 - PCIE PME and message detect register */
0069     __be32  pex_pme_mes_disr;   /* 0x.024 - PCIE PME and message disable register */
0070     __be32  pex_pme_mes_ier;    /* 0x.028 - PCIE PME and message interrupt enable register */
0071     __be32  pex_pmcr;       /* 0x.02c - PCIE power management command register */
0072     u8  res3[3016];
0073     __be32  block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
0074     __be32  block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
0075
0076 /* PCI/PCI Express outbound window 0-4
0077  * Window 0 is the default window and is the only window enabled upon reset.
0078  * The default outbound register set is used when a transaction misses
0079  * in all of the other outbound windows.
0080  */
0081     struct pci_outbound_window_regs pow[5];
0082     u8  res14[96];
0083     struct pci_inbound_window_regs  pmit;   /* 0xd00 - 0xd9c Inbound MSI */
0084     u8  res6[96];
0085 /* PCI/PCI Express inbound window 3-0
0086  * inbound window 1 supports only a 32-bit base address and does not
0087  * define an inbound window base extended address register.
0088  */
0089     struct pci_inbound_window_regs piw[4];
0090
0091     __be32  pex_err_dr;     /* 0x.e00 - PCI/PCIE error detect register */
0092     u8  res21[4];
0093     __be32  pex_err_en;     /* 0x.e08 - PCI/PCIE error interrupt enable register */
0094     u8  res22[4];
0095     __be32  pex_err_disr;       /* 0x.e10 - PCI/PCIE error disable register */
0096     u8  res23[12];
0097     __be32  pex_err_cap_stat;   /* 0x.e20 - PCI/PCIE error capture status register */
0098     u8  res24[4];
0099     __be32  pex_err_cap_r0;     /* 0x.e28 - PCIE error capture register 0 */
0100     __be32  pex_err_cap_r1;     /* 0x.e2c - PCIE error capture register 0 */
0101     __be32  pex_err_cap_r2;     /* 0x.e30 - PCIE error capture register 0 */
0102     __be32  pex_err_cap_r3;     /* 0x.e34 - PCIE error capture register 0 */
0103     u8  res_e38[200];
0104     __be32  pdb_stat;       /* 0x.f00 - PCIE Debug Status */
0105     u8  res_f04[16];
0106     __be32  pex_csr0;       /* 0x.f14 - PEX Control/Status register 0*/
0107 #define PEX_CSR0_LTSSM_MASK 0xFC
0108 #define PEX_CSR0_LTSSM_SHIFT    2
0109 #define PEX_CSR0_LTSSM_L0   0x11
0110     __be32  pex_csr1;       /* 0x.f18 - PEX Control/Status register 1*/
0111     u8  res_f1c[228];
0112
0113 };
0114
0115 extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
0116 extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
0117 extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
0118 extern int mpc83xx_add_bridge(struct device_node *dev);
0119 u64 fsl_pci_immrbar_base(struct pci_controller *hose);
0120
0121 extern struct device_node *fsl_pci_primary;
0122
0123 #ifdef CONFIG_PCI
0124 void __init fsl_pci_assign_primary(void);
0125 #else
0126 static inline void fsl_pci_assign_primary(void) {}
0127 #endif
0128
0129 #ifdef CONFIG_FSL_PCI
0130 extern int fsl_pci_mcheck_exception(struct pt_regs *);
0131 #else
0132 static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
0133 #endif
0134
0135 #endif /* __POWERPC_FSL_PCI_H */
0136 #endif /* __KERNEL__ */