Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * MPC83xx/85xx/86xx PCI/PCIE support routing.
0004  *
0005  * Copyright 2007-2012 Freescale Semiconductor, Inc.
0006  * Copyright 2008-2009 MontaVista Software, Inc.
0007  *
0008  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
0009  * Recode: ZHANG WEI <wei.zhang@freescale.com>
0010  * Rewrite the routing for Frescale PCI and PCI Express
0011  *  Roy Zang <tie-fei.zang@freescale.com>
0012  * MPC83xx PCI-Express support:
0013  *  Tony Li <tony.li@freescale.com>
0014  *  Anton Vorontsov <avorontsov@ru.mvista.com>
0015  */
0016 #include <linux/kernel.h>
0017 #include <linux/pci.h>
0018 #include <linux/delay.h>
0019 #include <linux/string.h>
0020 #include <linux/fsl/edac.h>
0021 #include <linux/init.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/memblock.h>
0024 #include <linux/log2.h>
0025 #include <linux/of_address.h>
0026 #include <linux/of_irq.h>
0027 #include <linux/platform_device.h>
0028 #include <linux/slab.h>
0029 #include <linux/suspend.h>
0030 #include <linux/syscore_ops.h>
0031 #include <linux/uaccess.h>
0032 
0033 #include <asm/io.h>
0034 #include <asm/pci-bridge.h>
0035 #include <asm/ppc-pci.h>
0036 #include <asm/machdep.h>
0037 #include <asm/mpc85xx.h>
0038 #include <asm/disassemble.h>
0039 #include <asm/ppc-opcode.h>
0040 #include <asm/swiotlb.h>
0041 #include <asm/setup.h>
0042 #include <sysdev/fsl_soc.h>
0043 #include <sysdev/fsl_pci.h>
0044 
0045 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
0046 
0047 static void quirk_fsl_pcie_early(struct pci_dev *dev)
0048 {
0049     u8 hdr_type;
0050 
0051     /* if we aren't a PCIe don't bother */
0052     if (!pci_is_pcie(dev))
0053         return;
0054 
0055     /* if we aren't in host mode don't bother */
0056     pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
0057     if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
0058         return;
0059 
0060     dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
0061     fsl_pcie_bus_fixup = 1;
0062     return;
0063 }
0064 
0065 static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
0066                     int, int, u32 *);
0067 
0068 static int fsl_pcie_check_link(struct pci_controller *hose)
0069 {
0070     u32 val = 0;
0071 
0072     if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
0073         if (hose->ops->read == fsl_indirect_read_config)
0074             __indirect_read_config(hose, hose->first_busno, 0,
0075                            PCIE_LTSSM, 4, &val);
0076         else
0077             early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
0078         if (val < PCIE_LTSSM_L0)
0079             return 1;
0080     } else {
0081         struct ccsr_pci __iomem *pci = hose->private_data;
0082         /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
0083         val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
0084                 >> PEX_CSR0_LTSSM_SHIFT;
0085         if (val != PEX_CSR0_LTSSM_L0)
0086             return 1;
0087     }
0088 
0089     return 0;
0090 }
0091 
0092 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
0093                     int offset, int len, u32 *val)
0094 {
0095     struct pci_controller *hose = pci_bus_to_host(bus);
0096 
0097     if (fsl_pcie_check_link(hose))
0098         hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
0099     else
0100         hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
0101 
0102     return indirect_read_config(bus, devfn, offset, len, val);
0103 }
0104 
0105 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
0106 
0107 static struct pci_ops fsl_indirect_pcie_ops =
0108 {
0109     .read = fsl_indirect_read_config,
0110     .write = indirect_write_config,
0111 };
0112 
0113 static u64 pci64_dma_offset;
0114 
0115 #ifdef CONFIG_SWIOTLB
0116 static void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev)
0117 {
0118     struct pci_controller *hose = pci_bus_to_host(pdev->bus);
0119 
0120     pdev->dev.bus_dma_limit =
0121         hose->dma_window_base_cur + hose->dma_window_size - 1;
0122 }
0123 
0124 static void setup_swiotlb_ops(struct pci_controller *hose)
0125 {
0126     if (ppc_swiotlb_enable)
0127         hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;
0128 }
0129 #else
0130 static inline void setup_swiotlb_ops(struct pci_controller *hose) {}
0131 #endif
0132 
0133 static void fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
0134 {
0135     /*
0136      * Fix up PCI devices that are able to DMA to the large inbound
0137      * mapping that allows addressing any RAM address from across PCI.
0138      */
0139     if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) {
0140         dev->bus_dma_limit = 0;
0141         dev->archdata.dma_offset = pci64_dma_offset;
0142     }
0143 }
0144 
0145 static int setup_one_atmu(struct ccsr_pci __iomem *pci,
0146     unsigned int index, const struct resource *res,
0147     resource_size_t offset)
0148 {
0149     resource_size_t pci_addr = res->start - offset;
0150     resource_size_t phys_addr = res->start;
0151     resource_size_t size = resource_size(res);
0152     u32 flags = 0x80044000; /* enable & mem R/W */
0153     unsigned int i;
0154 
0155     pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
0156         (u64)res->start, (u64)size);
0157 
0158     if (res->flags & IORESOURCE_PREFETCH)
0159         flags |= 0x10000000; /* enable relaxed ordering */
0160 
0161     for (i = 0; size > 0; i++) {
0162         unsigned int bits = min_t(u32, ilog2(size),
0163                     __ffs(pci_addr | phys_addr));
0164 
0165         if (index + i >= 5)
0166             return -1;
0167 
0168         out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
0169         out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
0170         out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
0171         out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
0172 
0173         pci_addr += (resource_size_t)1U << bits;
0174         phys_addr += (resource_size_t)1U << bits;
0175         size -= (resource_size_t)1U << bits;
0176     }
0177 
0178     return i;
0179 }
0180 
0181 static bool is_kdump(void)
0182 {
0183     struct device_node *node;
0184 
0185     node = of_find_node_by_type(NULL, "memory");
0186     if (!node) {
0187         WARN_ON_ONCE(1);
0188         return false;
0189     }
0190 
0191     return of_property_read_bool(node, "linux,usable-memory");
0192 }
0193 
0194 /* atmu setup for fsl pci/pcie controller */
0195 static void setup_pci_atmu(struct pci_controller *hose)
0196 {
0197     struct ccsr_pci __iomem *pci = hose->private_data;
0198     int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
0199     u64 mem, sz, paddr_hi = 0;
0200     u64 offset = 0, paddr_lo = ULLONG_MAX;
0201     u32 pcicsrbar = 0, pcicsrbar_sz;
0202     u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
0203             PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
0204     const u64 *reg;
0205     int len;
0206     bool setup_inbound;
0207 
0208     /*
0209      * If this is kdump, we don't want to trigger a bunch of PCI
0210      * errors by closing the window on in-flight DMA.
0211      *
0212      * We still run most of the function's logic so that things like
0213      * hose->dma_window_size still get set.
0214      */
0215     setup_inbound = !is_kdump();
0216 
0217     if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) {
0218         /*
0219          * BSC9132 Rev1.0 has an issue where all the PEX inbound
0220          * windows have implemented the default target value as 0xf
0221          * for CCSR space.In all Freescale legacy devices the target
0222          * of 0xf is reserved for local memory space. 9132 Rev1.0
0223          * now has local memory space mapped to target 0x0 instead of
0224          * 0xf. Hence adding a workaround to remove the target 0xf
0225          * defined for memory space from Inbound window attributes.
0226          */
0227         piwar &= ~PIWAR_TGI_LOCAL;
0228     }
0229 
0230     if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
0231         if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
0232             win_idx = 2;
0233             start_idx = 0;
0234             end_idx = 3;
0235         }
0236     }
0237 
0238     /* Disable all windows (except powar0 since it's ignored) */
0239     for(i = 1; i < 5; i++)
0240         out_be32(&pci->pow[i].powar, 0);
0241 
0242     if (setup_inbound) {
0243         for (i = start_idx; i < end_idx; i++)
0244             out_be32(&pci->piw[i].piwar, 0);
0245     }
0246 
0247     /* Setup outbound MEM window */
0248     for(i = 0, j = 1; i < 3; i++) {
0249         if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
0250             continue;
0251 
0252         paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
0253         paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
0254 
0255         /* We assume all memory resources have the same offset */
0256         offset = hose->mem_offset[i];
0257         n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
0258 
0259         if (n < 0 || j >= 5) {
0260             pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
0261             hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
0262         } else
0263             j += n;
0264     }
0265 
0266     /* Setup outbound IO window */
0267     if (hose->io_resource.flags & IORESOURCE_IO) {
0268         if (j >= 5) {
0269             pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
0270         } else {
0271             pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
0272                  "phy base 0x%016llx.\n",
0273                  (u64)hose->io_resource.start,
0274                  (u64)resource_size(&hose->io_resource),
0275                  (u64)hose->io_base_phys);
0276             out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
0277             out_be32(&pci->pow[j].potear, 0);
0278             out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
0279             /* Enable, IO R/W */
0280             out_be32(&pci->pow[j].powar, 0x80088000
0281                 | (ilog2(hose->io_resource.end
0282                 - hose->io_resource.start + 1) - 1));
0283         }
0284     }
0285 
0286     /* convert to pci address space */
0287     paddr_hi -= offset;
0288     paddr_lo -= offset;
0289 
0290     if (paddr_hi == paddr_lo) {
0291         pr_err("%pOF: No outbound window space\n", hose->dn);
0292         return;
0293     }
0294 
0295     if (paddr_lo == 0) {
0296         pr_err("%pOF: No space for inbound window\n", hose->dn);
0297         return;
0298     }
0299 
0300     /* setup PCSRBAR/PEXCSRBAR */
0301     early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
0302     early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
0303     pcicsrbar_sz = ~pcicsrbar_sz + 1;
0304 
0305     if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
0306         (paddr_lo > 0x100000000ull))
0307         pcicsrbar = 0x100000000ull - pcicsrbar_sz;
0308     else
0309         pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
0310     early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
0311 
0312     paddr_lo = min(paddr_lo, (u64)pcicsrbar);
0313 
0314     pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar);
0315 
0316     /* Setup inbound mem window */
0317     mem = memblock_end_of_DRAM();
0318     pr_info("%s: end of DRAM %llx\n", __func__, mem);
0319 
0320     /*
0321      * The msi-address-64 property, if it exists, indicates the physical
0322      * address of the MSIIR register.  Normally, this register is located
0323      * inside CCSR, so the ATMU that covers all of CCSR is used. But if
0324      * this property exists, then we normally need to create a new ATMU
0325      * for it.  For now, however, we cheat.  The only entity that creates
0326      * this property is the Freescale hypervisor, and the address is
0327      * specified in the partition configuration.  Typically, the address
0328      * is located in the page immediately after the end of DDR.  If so, we
0329      * can avoid allocating a new ATMU by extending the DDR ATMU by one
0330      * page.
0331      */
0332     reg = of_get_property(hose->dn, "msi-address-64", &len);
0333     if (reg && (len == sizeof(u64))) {
0334         u64 address = be64_to_cpup(reg);
0335 
0336         if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
0337             pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn);
0338             mem += PAGE_SIZE;
0339         } else {
0340             /* TODO: Create a new ATMU for MSIIR */
0341             pr_warn("%pOF: msi-address-64 address of %llx is "
0342                 "unsupported\n", hose->dn, address);
0343         }
0344     }
0345 
0346     sz = min(mem, paddr_lo);
0347     mem_log = ilog2(sz);
0348 
0349     /* PCIe can overmap inbound & outbound since RX & TX are separated */
0350     if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
0351         /* Size window to exact size if power-of-two or one size up */
0352         if ((1ull << mem_log) != mem) {
0353             mem_log++;
0354             if ((1ull << mem_log) > mem)
0355                 pr_info("%pOF: Setting PCI inbound window "
0356                     "greater than memory size\n", hose->dn);
0357         }
0358 
0359         piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
0360 
0361         if (setup_inbound) {
0362             /* Setup inbound memory window */
0363             out_be32(&pci->piw[win_idx].pitar,  0x00000000);
0364             out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
0365             out_be32(&pci->piw[win_idx].piwar,  piwar);
0366         }
0367 
0368         win_idx--;
0369         hose->dma_window_base_cur = 0x00000000;
0370         hose->dma_window_size = (resource_size_t)sz;
0371 
0372         /*
0373          * if we have >4G of memory setup second PCI inbound window to
0374          * let devices that are 64-bit address capable to work w/o
0375          * SWIOTLB and access the full range of memory
0376          */
0377         if (sz != mem) {
0378             mem_log = ilog2(mem);
0379 
0380             /* Size window up if we dont fit in exact power-of-2 */
0381             if ((1ull << mem_log) != mem)
0382                 mem_log++;
0383 
0384             piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
0385             pci64_dma_offset = 1ULL << mem_log;
0386 
0387             if (setup_inbound) {
0388                 /* Setup inbound memory window */
0389                 out_be32(&pci->piw[win_idx].pitar,  0x00000000);
0390                 out_be32(&pci->piw[win_idx].piwbear,
0391                         pci64_dma_offset >> 44);
0392                 out_be32(&pci->piw[win_idx].piwbar,
0393                         pci64_dma_offset >> 12);
0394                 out_be32(&pci->piw[win_idx].piwar,  piwar);
0395             }
0396 
0397             /*
0398              * install our own dma_set_mask handler to fixup dma_ops
0399              * and dma_offset
0400              */
0401             ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
0402 
0403             pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn);
0404         }
0405     } else {
0406         u64 paddr = 0;
0407 
0408         if (setup_inbound) {
0409             /* Setup inbound memory window */
0410             out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
0411             out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
0412             out_be32(&pci->piw[win_idx].piwar,
0413                  (piwar | (mem_log - 1)));
0414         }
0415 
0416         win_idx--;
0417         paddr += 1ull << mem_log;
0418         sz -= 1ull << mem_log;
0419 
0420         if (sz) {
0421             mem_log = ilog2(sz);
0422             piwar |= (mem_log - 1);
0423 
0424             if (setup_inbound) {
0425                 out_be32(&pci->piw[win_idx].pitar,
0426                      paddr >> 12);
0427                 out_be32(&pci->piw[win_idx].piwbar,
0428                      paddr >> 12);
0429                 out_be32(&pci->piw[win_idx].piwar, piwar);
0430             }
0431 
0432             win_idx--;
0433             paddr += 1ull << mem_log;
0434         }
0435 
0436         hose->dma_window_base_cur = 0x00000000;
0437         hose->dma_window_size = (resource_size_t)paddr;
0438     }
0439 
0440     if (hose->dma_window_size < mem) {
0441 #ifdef CONFIG_SWIOTLB
0442         ppc_swiotlb_enable = 1;
0443 #else
0444         pr_err("%pOF: ERROR: Memory size exceeds PCI ATMU ability to "
0445             "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
0446              hose->dn);
0447 #endif
0448         /* adjusting outbound windows could reclaim space in mem map */
0449         if (paddr_hi < 0xffffffffull)
0450             pr_warn("%pOF: WARNING: Outbound window cfg leaves "
0451                 "gaps in memory map. Adjusting the memory map "
0452                 "could reduce unnecessary bounce buffering.\n",
0453                 hose->dn);
0454 
0455         pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn,
0456             (u64)hose->dma_window_size);
0457     }
0458 }
0459 
0460 static void setup_pci_cmd(struct pci_controller *hose)
0461 {
0462     u16 cmd;
0463     int cap_x;
0464 
0465     early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
0466     cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
0467         | PCI_COMMAND_IO;
0468     early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
0469 
0470     cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
0471     if (cap_x) {
0472         int pci_x_cmd = cap_x + PCI_X_CMD;
0473         cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
0474             | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
0475         early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
0476     } else {
0477         early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
0478     }
0479 }
0480 
0481 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
0482 {
0483     struct pci_controller *hose = pci_bus_to_host(bus);
0484     int i, is_pcie = 0, no_link;
0485 
0486     /* The root complex bridge comes up with bogus resources,
0487      * we copy the PHB ones in.
0488      *
0489      * With the current generic PCI code, the PHB bus no longer
0490      * has bus->resource[0..4] set, so things are a bit more
0491      * tricky.
0492      */
0493 
0494     if (fsl_pcie_bus_fixup)
0495         is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
0496     no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
0497 
0498     if (bus->parent == hose->bus && (is_pcie || no_link)) {
0499         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
0500             struct resource *res = bus->resource[i];
0501             struct resource *par;
0502 
0503             if (!res)
0504                 continue;
0505             if (i == 0)
0506                 par = &hose->io_resource;
0507             else if (i < 4)
0508                 par = &hose->mem_resources[i-1];
0509             else par = NULL;
0510 
0511             res->start = par ? par->start : 0;
0512             res->end   = par ? par->end   : 0;
0513             res->flags = par ? par->flags : 0;
0514         }
0515     }
0516 }
0517 
0518 int fsl_add_bridge(struct platform_device *pdev, int is_primary)
0519 {
0520     int len;
0521     struct pci_controller *hose;
0522     struct resource rsrc;
0523     const int *bus_range;
0524     u8 hdr_type, progif;
0525     u32 class_code;
0526     struct device_node *dev;
0527     struct ccsr_pci __iomem *pci;
0528     u16 temp;
0529     u32 svr = mfspr(SPRN_SVR);
0530 
0531     dev = pdev->dev.of_node;
0532 
0533     if (!of_device_is_available(dev)) {
0534         pr_warn("%pOF: disabled\n", dev);
0535         return -ENODEV;
0536     }
0537 
0538     pr_debug("Adding PCI host bridge %pOF\n", dev);
0539 
0540     /* Fetch host bridge registers address */
0541     if (of_address_to_resource(dev, 0, &rsrc)) {
0542         printk(KERN_WARNING "Can't get pci register base!");
0543         return -ENOMEM;
0544     }
0545 
0546     /* Get bus range if any */
0547     bus_range = of_get_property(dev, "bus-range", &len);
0548     if (bus_range == NULL || len < 2 * sizeof(int))
0549         printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
0550             " bus 0\n", dev);
0551 
0552     pci_add_flags(PCI_REASSIGN_ALL_BUS);
0553     hose = pcibios_alloc_controller(dev);
0554     if (!hose)
0555         return -ENOMEM;
0556 
0557     /* set platform device as the parent */
0558     hose->parent = &pdev->dev;
0559     hose->first_busno = bus_range ? bus_range[0] : 0x0;
0560     hose->last_busno = bus_range ? bus_range[1] : 0xff;
0561 
0562     pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
0563          (u64)rsrc.start, (u64)resource_size(&rsrc));
0564 
0565     pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
0566     if (!hose->private_data)
0567         goto no_bridge;
0568 
0569     setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
0570                PPC_INDIRECT_TYPE_BIG_ENDIAN);
0571 
0572     if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
0573         hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
0574 
0575     if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
0576         /* use fsl_indirect_read_config for PCIe */
0577         hose->ops = &fsl_indirect_pcie_ops;
0578         /* For PCIE read HEADER_TYPE to identify controller mode */
0579         early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
0580         if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
0581             goto no_bridge;
0582 
0583     } else {
0584         /* For PCI read PROG to identify controller mode */
0585         early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
0586         if ((progif & 1) &&
0587             !of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
0588             goto no_bridge;
0589     }
0590 
0591     setup_pci_cmd(hose);
0592 
0593     /* check PCI express link status */
0594     if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
0595         hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
0596             PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
0597         if (fsl_pcie_check_link(hose))
0598             hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
0599         /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
0600         if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
0601             early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
0602             class_code &= 0xff;
0603             class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
0604             early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
0605         }
0606     } else {
0607         /*
0608          * Set PBFR(PCI Bus Function Register)[10] = 1 to
0609          * disable the combining of crossing cacheline
0610          * boundary requests into one burst transaction.
0611          * PCI-X operation is not affected.
0612          * Fix erratum PCI 5 on MPC8548
0613          */
0614 #define PCI_BUS_FUNCTION 0x44
0615 #define PCI_BUS_FUNCTION_MDS 0x400  /* Master disable streaming */
0616         if (((SVR_SOC_VER(svr) == SVR_8543) ||
0617              (SVR_SOC_VER(svr) == SVR_8545) ||
0618              (SVR_SOC_VER(svr) == SVR_8547) ||
0619              (SVR_SOC_VER(svr) == SVR_8548)) &&
0620             !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
0621             early_read_config_word(hose, 0, 0,
0622                     PCI_BUS_FUNCTION, &temp);
0623             temp |= PCI_BUS_FUNCTION_MDS;
0624             early_write_config_word(hose, 0, 0,
0625                     PCI_BUS_FUNCTION, temp);
0626         }
0627     }
0628 
0629     printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
0630         "Firmware bus number: %d->%d\n",
0631         (unsigned long long)rsrc.start, hose->first_busno,
0632         hose->last_busno);
0633 
0634     pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
0635         hose, hose->cfg_addr, hose->cfg_data);
0636 
0637     /* Interpret the "ranges" property */
0638     /* This also maps the I/O region and sets isa_io/mem_base */
0639     pci_process_bridge_OF_ranges(hose, dev, is_primary);
0640 
0641     /* Setup PEX window registers */
0642     setup_pci_atmu(hose);
0643 
0644     /* Set up controller operations */
0645     setup_swiotlb_ops(hose);
0646 
0647     return 0;
0648 
0649 no_bridge:
0650     iounmap(hose->private_data);
0651     /* unmap cfg_data & cfg_addr separately if not on same page */
0652     if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
0653         ((unsigned long)hose->cfg_addr & PAGE_MASK))
0654         iounmap(hose->cfg_data);
0655     iounmap(hose->cfg_addr);
0656     pcibios_free_controller(hose);
0657     return -ENODEV;
0658 }
0659 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
0660 
0661 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
0662             quirk_fsl_pcie_early);
0663 
0664 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
0665 struct mpc83xx_pcie_priv {
0666     void __iomem *cfg_type0;
0667     void __iomem *cfg_type1;
0668     u32 dev_base;
0669 };
0670 
0671 struct pex_inbound_window {
0672     u32 ar;
0673     u32 tar;
0674     u32 barl;
0675     u32 barh;
0676 };
0677 
0678 /*
0679  * With the convention of u-boot, the PCIE outbound window 0 serves
0680  * as configuration transactions outbound.
0681  */
0682 #define PEX_OUTWIN0_BAR     0xCA4
0683 #define PEX_OUTWIN0_TAL     0xCA8
0684 #define PEX_OUTWIN0_TAH     0xCAC
0685 #define PEX_RC_INWIN_BASE   0xE60
0686 #define PEX_RCIWARn_EN      0x1
0687 
0688 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
0689 {
0690     struct pci_controller *hose = pci_bus_to_host(bus);
0691 
0692     if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
0693         return PCIBIOS_DEVICE_NOT_FOUND;
0694     /*
0695      * Workaround for the HW bug: for Type 0 configure transactions the
0696      * PCI-E controller does not check the device number bits and just
0697      * assumes that the device number bits are 0.
0698      */
0699     if (bus->number == hose->first_busno ||
0700             bus->primary == hose->first_busno) {
0701         if (devfn & 0xf8)
0702             return PCIBIOS_DEVICE_NOT_FOUND;
0703     }
0704 
0705     if (ppc_md.pci_exclude_device) {
0706         if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
0707             return PCIBIOS_DEVICE_NOT_FOUND;
0708     }
0709 
0710     return PCIBIOS_SUCCESSFUL;
0711 }
0712 
0713 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
0714                         unsigned int devfn, int offset)
0715 {
0716     struct pci_controller *hose = pci_bus_to_host(bus);
0717     struct mpc83xx_pcie_priv *pcie = hose->dn->data;
0718     u32 dev_base = bus->number << 24 | devfn << 16;
0719     int ret;
0720 
0721     ret = mpc83xx_pcie_exclude_device(bus, devfn);
0722     if (ret)
0723         return NULL;
0724 
0725     offset &= 0xfff;
0726 
0727     /* Type 0 */
0728     if (bus->number == hose->first_busno)
0729         return pcie->cfg_type0 + offset;
0730 
0731     if (pcie->dev_base == dev_base)
0732         goto mapped;
0733 
0734     out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
0735 
0736     pcie->dev_base = dev_base;
0737 mapped:
0738     return pcie->cfg_type1 + offset;
0739 }
0740 
0741 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
0742                      int offset, int len, u32 val)
0743 {
0744     struct pci_controller *hose = pci_bus_to_host(bus);
0745 
0746     /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
0747     if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
0748         val &= 0xffffff00;
0749 
0750     return pci_generic_config_write(bus, devfn, offset, len, val);
0751 }
0752 
0753 static struct pci_ops mpc83xx_pcie_ops = {
0754     .map_bus = mpc83xx_pcie_remap_cfg,
0755     .read = pci_generic_config_read,
0756     .write = mpc83xx_pcie_write_config,
0757 };
0758 
0759 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
0760                      struct resource *reg)
0761 {
0762     struct mpc83xx_pcie_priv *pcie;
0763     u32 cfg_bar;
0764     int ret = -ENOMEM;
0765 
0766     pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
0767     if (!pcie)
0768         return ret;
0769 
0770     pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
0771     if (!pcie->cfg_type0)
0772         goto err0;
0773 
0774     cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
0775     if (!cfg_bar) {
0776         /* PCI-E isn't configured. */
0777         ret = -ENODEV;
0778         goto err1;
0779     }
0780 
0781     pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
0782     if (!pcie->cfg_type1)
0783         goto err1;
0784 
0785     WARN_ON(hose->dn->data);
0786     hose->dn->data = pcie;
0787     hose->ops = &mpc83xx_pcie_ops;
0788     hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
0789 
0790     out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
0791     out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
0792 
0793     if (fsl_pcie_check_link(hose))
0794         hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
0795 
0796     return 0;
0797 err1:
0798     iounmap(pcie->cfg_type0);
0799 err0:
0800     kfree(pcie);
0801     return ret;
0802 
0803 }
0804 
0805 int __init mpc83xx_add_bridge(struct device_node *dev)
0806 {
0807     int ret;
0808     int len;
0809     struct pci_controller *hose;
0810     struct resource rsrc_reg;
0811     struct resource rsrc_cfg;
0812     const int *bus_range;
0813     int primary;
0814 
0815     is_mpc83xx_pci = 1;
0816 
0817     if (!of_device_is_available(dev)) {
0818         pr_warn("%pOF: disabled by the firmware.\n",
0819             dev);
0820         return -ENODEV;
0821     }
0822     pr_debug("Adding PCI host bridge %pOF\n", dev);
0823 
0824     /* Fetch host bridge registers address */
0825     if (of_address_to_resource(dev, 0, &rsrc_reg)) {
0826         printk(KERN_WARNING "Can't get pci register base!\n");
0827         return -ENOMEM;
0828     }
0829 
0830     memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
0831 
0832     if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
0833         printk(KERN_WARNING
0834             "No pci config register base in dev tree, "
0835             "using default\n");
0836         /*
0837          * MPC83xx supports up to two host controllers
0838          *  one at 0x8500 has config space registers at 0x8300
0839          *  one at 0x8600 has config space registers at 0x8380
0840          */
0841         if ((rsrc_reg.start & 0xfffff) == 0x8500)
0842             rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
0843         else if ((rsrc_reg.start & 0xfffff) == 0x8600)
0844             rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
0845     }
0846     /*
0847      * Controller at offset 0x8500 is primary
0848      */
0849     if ((rsrc_reg.start & 0xfffff) == 0x8500)
0850         primary = 1;
0851     else
0852         primary = 0;
0853 
0854     /* Get bus range if any */
0855     bus_range = of_get_property(dev, "bus-range", &len);
0856     if (bus_range == NULL || len < 2 * sizeof(int)) {
0857         printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
0858                " bus 0\n", dev);
0859     }
0860 
0861     pci_add_flags(PCI_REASSIGN_ALL_BUS);
0862     hose = pcibios_alloc_controller(dev);
0863     if (!hose)
0864         return -ENOMEM;
0865 
0866     hose->first_busno = bus_range ? bus_range[0] : 0;
0867     hose->last_busno = bus_range ? bus_range[1] : 0xff;
0868 
0869     if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
0870         ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
0871         if (ret)
0872             goto err0;
0873     } else {
0874         setup_indirect_pci(hose, rsrc_cfg.start,
0875                    rsrc_cfg.start + 4, 0);
0876     }
0877 
0878     printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
0879            "Firmware bus number: %d->%d\n",
0880            (unsigned long long)rsrc_reg.start, hose->first_busno,
0881            hose->last_busno);
0882 
0883     pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
0884         hose, hose->cfg_addr, hose->cfg_data);
0885 
0886     /* Interpret the "ranges" property */
0887     /* This also maps the I/O region and sets isa_io/mem_base */
0888     pci_process_bridge_OF_ranges(hose, dev, primary);
0889 
0890     return 0;
0891 err0:
0892     pcibios_free_controller(hose);
0893     return ret;
0894 }
0895 #endif /* CONFIG_PPC_83xx */
0896 
0897 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
0898 {
0899 #ifdef CONFIG_PPC_83xx
0900     if (is_mpc83xx_pci) {
0901         struct mpc83xx_pcie_priv *pcie = hose->dn->data;
0902         struct pex_inbound_window *in;
0903         int i;
0904 
0905         /* Walk the Root Complex Inbound windows to match IMMR base */
0906         in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
0907         for (i = 0; i < 4; i++) {
0908             /* not enabled, skip */
0909             if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN))
0910                 continue;
0911 
0912             if (get_immrbase() == in_le32(&in[i].tar))
0913                 return (u64)in_le32(&in[i].barh) << 32 |
0914                         in_le32(&in[i].barl);
0915         }
0916 
0917         printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
0918     }
0919 #endif
0920 
0921 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
0922     if (!is_mpc83xx_pci) {
0923         u32 base;
0924 
0925         pci_bus_read_config_dword(hose->bus,
0926             PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
0927 
0928         /*
0929          * For PEXCSRBAR, bit 3-0 indicate prefetchable and
0930          * address type. So when getting base address, these
0931          * bits should be masked
0932          */
0933         base &= PCI_BASE_ADDRESS_MEM_MASK;
0934 
0935         return base;
0936     }
0937 #endif
0938 
0939     return 0;
0940 }
0941 
0942 #ifdef CONFIG_E500
0943 static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
0944 {
0945     unsigned int rd, ra, rb, d;
0946 
0947     rd = get_rt(inst);
0948     ra = get_ra(inst);
0949     rb = get_rb(inst);
0950     d = get_d(inst);
0951 
0952     switch (get_op(inst)) {
0953     case 31:
0954         switch (get_xop(inst)) {
0955         case OP_31_XOP_LWZX:
0956         case OP_31_XOP_LWBRX:
0957             regs->gpr[rd] = 0xffffffff;
0958             break;
0959 
0960         case OP_31_XOP_LWZUX:
0961             regs->gpr[rd] = 0xffffffff;
0962             regs->gpr[ra] += regs->gpr[rb];
0963             break;
0964 
0965         case OP_31_XOP_LBZX:
0966             regs->gpr[rd] = 0xff;
0967             break;
0968 
0969         case OP_31_XOP_LBZUX:
0970             regs->gpr[rd] = 0xff;
0971             regs->gpr[ra] += regs->gpr[rb];
0972             break;
0973 
0974         case OP_31_XOP_LHZX:
0975         case OP_31_XOP_LHBRX:
0976             regs->gpr[rd] = 0xffff;
0977             break;
0978 
0979         case OP_31_XOP_LHZUX:
0980             regs->gpr[rd] = 0xffff;
0981             regs->gpr[ra] += regs->gpr[rb];
0982             break;
0983 
0984         case OP_31_XOP_LHAX:
0985             regs->gpr[rd] = ~0UL;
0986             break;
0987 
0988         case OP_31_XOP_LHAUX:
0989             regs->gpr[rd] = ~0UL;
0990             regs->gpr[ra] += regs->gpr[rb];
0991             break;
0992 
0993         default:
0994             return 0;
0995         }
0996         break;
0997 
0998     case OP_LWZ:
0999         regs->gpr[rd] = 0xffffffff;
1000         break;
1001 
1002     case OP_LWZU:
1003         regs->gpr[rd] = 0xffffffff;
1004         regs->gpr[ra] += (s16)d;
1005         break;
1006 
1007     case OP_LBZ:
1008         regs->gpr[rd] = 0xff;
1009         break;
1010 
1011     case OP_LBZU:
1012         regs->gpr[rd] = 0xff;
1013         regs->gpr[ra] += (s16)d;
1014         break;
1015 
1016     case OP_LHZ:
1017         regs->gpr[rd] = 0xffff;
1018         break;
1019 
1020     case OP_LHZU:
1021         regs->gpr[rd] = 0xffff;
1022         regs->gpr[ra] += (s16)d;
1023         break;
1024 
1025     case OP_LHA:
1026         regs->gpr[rd] = ~0UL;
1027         break;
1028 
1029     case OP_LHAU:
1030         regs->gpr[rd] = ~0UL;
1031         regs->gpr[ra] += (s16)d;
1032         break;
1033 
1034     default:
1035         return 0;
1036     }
1037 
1038     return 1;
1039 }
1040 
1041 static int is_in_pci_mem_space(phys_addr_t addr)
1042 {
1043     struct pci_controller *hose;
1044     struct resource *res;
1045     int i;
1046 
1047     list_for_each_entry(hose, &hose_list, list_node) {
1048         if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
1049             continue;
1050 
1051         for (i = 0; i < 3; i++) {
1052             res = &hose->mem_resources[i];
1053             if ((res->flags & IORESOURCE_MEM) &&
1054                 addr >= res->start && addr <= res->end)
1055                 return 1;
1056         }
1057     }
1058     return 0;
1059 }
1060 
1061 int fsl_pci_mcheck_exception(struct pt_regs *regs)
1062 {
1063     u32 inst;
1064     int ret;
1065     phys_addr_t addr = 0;
1066 
1067     /* Let KVM/QEMU deal with the exception */
1068     if (regs->msr & MSR_GS)
1069         return 0;
1070 
1071 #ifdef CONFIG_PHYS_64BIT
1072     addr = mfspr(SPRN_MCARU);
1073     addr <<= 32;
1074 #endif
1075     addr += mfspr(SPRN_MCAR);
1076 
1077     if (is_in_pci_mem_space(addr)) {
1078         if (user_mode(regs))
1079             ret = copy_from_user_nofault(&inst,
1080                     (void __user *)regs->nip, sizeof(inst));
1081         else
1082             ret = get_kernel_nofault(inst, (void *)regs->nip);
1083 
1084         if (!ret && mcheck_handle_load(regs, inst)) {
1085             regs_add_return_ip(regs, 4);
1086             return 1;
1087         }
1088     }
1089 
1090     return 0;
1091 }
1092 #endif
1093 
1094 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1095 static const struct of_device_id pci_ids[] = {
1096     { .compatible = "fsl,mpc8540-pci", },
1097     { .compatible = "fsl,mpc8548-pcie", },
1098     { .compatible = "fsl,mpc8610-pci", },
1099     { .compatible = "fsl,mpc8641-pcie", },
1100     { .compatible = "fsl,qoriq-pcie", },
1101     { .compatible = "fsl,qoriq-pcie-v2.1", },
1102     { .compatible = "fsl,qoriq-pcie-v2.2", },
1103     { .compatible = "fsl,qoriq-pcie-v2.3", },
1104     { .compatible = "fsl,qoriq-pcie-v2.4", },
1105     { .compatible = "fsl,qoriq-pcie-v3.0", },
1106 
1107     /*
1108      * The following entries are for compatibility with older device
1109      * trees.
1110      */
1111     { .compatible = "fsl,p1022-pcie", },
1112     { .compatible = "fsl,p4080-pcie", },
1113 
1114     {},
1115 };
1116 
1117 struct device_node *fsl_pci_primary;
1118 
1119 void __init fsl_pci_assign_primary(void)
1120 {
1121     struct device_node *np;
1122 
1123     /* Callers can specify the primary bus using other means. */
1124     if (fsl_pci_primary)
1125         return;
1126 
1127     /* If a PCI host bridge contains an ISA node, it's primary. */
1128     np = of_find_node_by_type(NULL, "isa");
1129     while ((fsl_pci_primary = of_get_parent(np))) {
1130         of_node_put(np);
1131         np = fsl_pci_primary;
1132 
1133         if (of_match_node(pci_ids, np) && of_device_is_available(np))
1134             return;
1135     }
1136 
1137     /*
1138      * If there's no PCI host bridge with ISA, arbitrarily
1139      * designate one as primary.  This can go away once
1140      * various bugs with primary-less systems are fixed.
1141      */
1142     for_each_matching_node(np, pci_ids) {
1143         if (of_device_is_available(np)) {
1144             fsl_pci_primary = np;
1145             of_node_put(np);
1146             return;
1147         }
1148     }
1149 }
1150 
1151 #ifdef CONFIG_PM_SLEEP
1152 static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
1153 {
1154     struct pci_controller *hose = dev_id;
1155     struct ccsr_pci __iomem *pci = hose->private_data;
1156     u32 dr;
1157 
1158     dr = in_be32(&pci->pex_pme_mes_dr);
1159     if (!dr)
1160         return IRQ_NONE;
1161 
1162     out_be32(&pci->pex_pme_mes_dr, dr);
1163 
1164     return IRQ_HANDLED;
1165 }
1166 
1167 static int fsl_pci_pme_probe(struct pci_controller *hose)
1168 {
1169     struct ccsr_pci __iomem *pci;
1170     struct pci_dev *dev;
1171     int pme_irq;
1172     int res;
1173     u16 pms;
1174 
1175     /* Get hose's pci_dev */
1176     dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
1177 
1178     /* PME Disable */
1179     pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1180     pms &= ~PCI_PM_CTRL_PME_ENABLE;
1181     pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1182 
1183     pme_irq = irq_of_parse_and_map(hose->dn, 0);
1184     if (!pme_irq) {
1185         dev_err(&dev->dev, "Failed to map PME interrupt.\n");
1186 
1187         return -ENXIO;
1188     }
1189 
1190     res = devm_request_irq(hose->parent, pme_irq,
1191             fsl_pci_pme_handle,
1192             IRQF_SHARED,
1193             "[PCI] PME", hose);
1194     if (res < 0) {
1195         dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq);
1196         irq_dispose_mapping(pme_irq);
1197 
1198         return -ENODEV;
1199     }
1200 
1201     pci = hose->private_data;
1202 
1203     /* Enable PTOD, ENL23D & EXL23D */
1204     clrbits32(&pci->pex_pme_mes_disr,
1205           PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1206 
1207     out_be32(&pci->pex_pme_mes_ier, 0);
1208     setbits32(&pci->pex_pme_mes_ier,
1209           PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1210 
1211     /* PME Enable */
1212     pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1213     pms |= PCI_PM_CTRL_PME_ENABLE;
1214     pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1215 
1216     return 0;
1217 }
1218 
1219 static void send_pme_turnoff_message(struct pci_controller *hose)
1220 {
1221     struct ccsr_pci __iomem *pci = hose->private_data;
1222     u32 dr;
1223     int i;
1224 
1225     /* Send PME_Turn_Off Message Request */
1226     setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
1227 
1228     /* Wait trun off done */
1229     for (i = 0; i < 150; i++) {
1230         dr = in_be32(&pci->pex_pme_mes_dr);
1231         if (dr) {
1232             out_be32(&pci->pex_pme_mes_dr, dr);
1233             break;
1234         }
1235 
1236         udelay(1000);
1237     }
1238 }
1239 
1240 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
1241 {
1242     send_pme_turnoff_message(hose);
1243 }
1244 
1245 static int fsl_pci_syscore_suspend(void)
1246 {
1247     struct pci_controller *hose, *tmp;
1248 
1249     list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1250         fsl_pci_syscore_do_suspend(hose);
1251 
1252     return 0;
1253 }
1254 
1255 static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
1256 {
1257     struct ccsr_pci __iomem *pci = hose->private_data;
1258     u32 dr;
1259     int i;
1260 
1261     /* Send Exit L2 State Message */
1262     setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
1263 
1264     /* Wait exit done */
1265     for (i = 0; i < 150; i++) {
1266         dr = in_be32(&pci->pex_pme_mes_dr);
1267         if (dr) {
1268             out_be32(&pci->pex_pme_mes_dr, dr);
1269             break;
1270         }
1271 
1272         udelay(1000);
1273     }
1274 
1275     setup_pci_atmu(hose);
1276 }
1277 
1278 static void fsl_pci_syscore_resume(void)
1279 {
1280     struct pci_controller *hose, *tmp;
1281 
1282     list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1283         fsl_pci_syscore_do_resume(hose);
1284 }
1285 
1286 static struct syscore_ops pci_syscore_pm_ops = {
1287     .suspend = fsl_pci_syscore_suspend,
1288     .resume = fsl_pci_syscore_resume,
1289 };
1290 #endif
1291 
1292 void fsl_pcibios_fixup_phb(struct pci_controller *phb)
1293 {
1294 #ifdef CONFIG_PM_SLEEP
1295     fsl_pci_pme_probe(phb);
1296 #endif
1297 }
1298 
1299 static int add_err_dev(struct platform_device *pdev)
1300 {
1301     struct platform_device *errdev;
1302     struct mpc85xx_edac_pci_plat_data pd = {
1303         .of_node = pdev->dev.of_node
1304     };
1305 
1306     errdev = platform_device_register_resndata(&pdev->dev,
1307                            "mpc85xx-pci-edac",
1308                            PLATFORM_DEVID_AUTO,
1309                            pdev->resource,
1310                            pdev->num_resources,
1311                            &pd, sizeof(pd));
1312 
1313     return PTR_ERR_OR_ZERO(errdev);
1314 }
1315 
1316 static int fsl_pci_probe(struct platform_device *pdev)
1317 {
1318     struct device_node *node;
1319     int ret;
1320 
1321     node = pdev->dev.of_node;
1322     ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
1323     if (ret)
1324         return ret;
1325 
1326     ret = add_err_dev(pdev);
1327     if (ret)
1328         dev_err(&pdev->dev, "couldn't register error device: %d\n",
1329             ret);
1330 
1331     return 0;
1332 }
1333 
1334 static struct platform_driver fsl_pci_driver = {
1335     .driver = {
1336         .name = "fsl-pci",
1337         .of_match_table = pci_ids,
1338     },
1339     .probe = fsl_pci_probe,
1340 };
1341 
1342 static int __init fsl_pci_init(void)
1343 {
1344 #ifdef CONFIG_PM_SLEEP
1345     register_syscore_ops(&pci_syscore_pm_ops);
1346 #endif
1347     return platform_driver_register(&fsl_pci_driver);
1348 }
1349 arch_initcall(fsl_pci_init);
1350 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!