powerpc/sysdev/fsl_msi.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
0004  *
0005  * Author: Tony Li <tony.li@freescale.com>
0006  *     Jason Jin <Jason.jin@freescale.com>
0007  */
0008 #ifndef _POWERPC_SYSDEV_FSL_MSI_H
0009 #define _POWERPC_SYSDEV_FSL_MSI_H
0010
0011 #include <linux/of.h>
0012 #include <asm/msi_bitmap.h>
0013
0014 #define NR_MSI_REG_MSIIR    8  /* MSIIR can index 8 MSI registers */
0015 #define NR_MSI_REG_MSIIR1   16 /* MSIIR1 can index 16 MSI registers */
0016 #define NR_MSI_REG_MAX      NR_MSI_REG_MSIIR1
0017 #define IRQS_PER_MSI_REG    32
0018 #define NR_MSI_IRQS_MAX (NR_MSI_REG_MAX * IRQS_PER_MSI_REG)
0019
0020 #define FSL_PIC_IP_MASK   0x0000000F
0021 #define FSL_PIC_IP_MPIC   0x00000001
0022 #define FSL_PIC_IP_IPIC   0x00000002
0023 #define FSL_PIC_IP_VMPIC  0x00000003
0024
0025 #define MSI_HW_ERRATA_ENDIAN 0x00000010
0026
0027 struct fsl_msi_cascade_data;
0028
0029 struct fsl_msi {
0030     struct irq_domain *irqhost;
0031
0032     unsigned long cascade_irq;
0033
0034     u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
0035     u32 ibs_shift; /* Shift of interrupt bit select */
0036     u32 srs_shift; /* Shift of the shared interrupt register select */
0037     void __iomem *msi_regs;
0038     u32 feature;
0039     struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX];
0040
0041     struct msi_bitmap bitmap;
0042
0043     struct list_head list;          /* support multiple MSI banks */
0044
0045     phandle phandle;
0046 };
0047
0048 #endif /* _POWERPC_SYSDEV_FSL_MSI_H */
0049