powerpc/sysdev/dart_iommu.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * arch/powerpc/sysdev/dart_iommu.c
0004  *
0005  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
0006  * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>,
0007  *                    IBM Corporation
0008  *
0009  * Based on pSeries_iommu.c:
0010  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
0011  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
0012  *
0013  * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
0014  */
0015
0016 #include <linux/init.h>
0017 #include <linux/types.h>
0018 #include <linux/mm.h>
0019 #include <linux/spinlock.h>
0020 #include <linux/string.h>
0021 #include <linux/pci.h>
0022 #include <linux/dma-mapping.h>
0023 #include <linux/vmalloc.h>
0024 #include <linux/suspend.h>
0025 #include <linux/memblock.h>
0026 #include <linux/gfp.h>
0027 #include <linux/kmemleak.h>
0028 #include <linux/of_address.h>
0029 #include <asm/io.h>
0030 #include <asm/iommu.h>
0031 #include <asm/pci-bridge.h>
0032 #include <asm/machdep.h>
0033 #include <asm/cacheflush.h>
0034 #include <asm/ppc-pci.h>
0035
0036 #include "dart.h"
0037
0038 /* DART table address and size */
0039 static u32 *dart_tablebase;
0040 static unsigned long dart_tablesize;
0041
0042 /* Mapped base address for the dart */
0043 static unsigned int __iomem *dart;
0044
0045 /* Dummy val that entries are set to when unused */
0046 static unsigned int dart_emptyval;
0047
0048 static struct iommu_table iommu_table_dart;
0049 static int iommu_table_dart_inited;
0050 static int dart_dirty;
0051 static int dart_is_u4;
0052
0053 #define DART_U4_BYPASS_BASE 0x8000000000ull
0054
0055 #define DBG(...)
0056
0057 static DEFINE_SPINLOCK(invalidate_lock);
0058
0059 static inline void dart_tlb_invalidate_all(void)
0060 {
0061     unsigned long l = 0;
0062     unsigned int reg, inv_bit;
0063     unsigned long limit;
0064     unsigned long flags;
0065
0066     spin_lock_irqsave(&invalidate_lock, flags);
0067
0068     DBG("dart: flush\n");
0069
0070     /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
0071      * control register and wait for it to clear.
0072      *
0073      * Gotcha: Sometimes, the DART won't detect that the bit gets
0074      * set. If so, clear it and set it again.
0075      */
0076
0077     limit = 0;
0078
0079     inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB;
0080 retry:
0081     l = 0;
0082     reg = DART_IN(DART_CNTL);
0083     reg |= inv_bit;
0084     DART_OUT(DART_CNTL, reg);
0085
0086     while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit))
0087         l++;
0088     if (l == (1L << limit)) {
0089         if (limit < 4) {
0090             limit++;
0091             reg = DART_IN(DART_CNTL);
0092             reg &= ~inv_bit;
0093             DART_OUT(DART_CNTL, reg);
0094             goto retry;
0095         } else
0096             panic("DART: TLB did not flush after waiting a long "
0097                   "time. Buggy U3 ?");
0098     }
0099
0100     spin_unlock_irqrestore(&invalidate_lock, flags);
0101 }
0102
0103 static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
0104 {
0105     unsigned int reg;
0106     unsigned int l, limit;
0107     unsigned long flags;
0108
0109     spin_lock_irqsave(&invalidate_lock, flags);
0110
0111     reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
0112         (bus_rpn & DART_CNTL_U4_IONE_MASK);
0113     DART_OUT(DART_CNTL, reg);
0114
0115     limit = 0;
0116 wait_more:
0117     l = 0;
0118     while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
0119         rmb();
0120         l++;
0121     }
0122
0123     if (l == (1L << limit)) {
0124         if (limit < 4) {
0125             limit++;
0126             goto wait_more;
0127         } else
0128             panic("DART: TLB did not flush after waiting a long "
0129                   "time. Buggy U4 ?");
0130     }
0131
0132     spin_unlock_irqrestore(&invalidate_lock, flags);
0133 }
0134
0135 static void dart_cache_sync(unsigned int *base, unsigned int count)
0136 {
0137     /*
0138      * We add 1 to the number of entries to flush, following a
0139      * comment in Darwin indicating that the memory controller
0140      * can prefetch unmapped memory under some circumstances.
0141      */
0142     unsigned long start = (unsigned long)base;
0143     unsigned long end = start + (count + 1) * sizeof(unsigned int);
0144     unsigned int tmp;
0145
0146     /* Perform a standard cache flush */
0147     flush_dcache_range(start, end);
0148
0149     /*
0150      * Perform the sequence described in the CPC925 manual to
0151      * ensure all the data gets to a point the cache incoherent
0152      * DART hardware will see.
0153      */
0154     asm volatile(" sync;"
0155              " isync;"
0156              " dcbf 0,%1;"
0157              " sync;"
0158              " isync;"
0159              " lwz %0,0(%1);"
0160              " isync" : "=r" (tmp) : "r" (end) : "memory");
0161 }
0162
0163 static void dart_flush(struct iommu_table *tbl)
0164 {
0165     mb();
0166     if (dart_dirty) {
0167         dart_tlb_invalidate_all();
0168         dart_dirty = 0;
0169     }
0170 }
0171
0172 static int dart_build(struct iommu_table *tbl, long index,
0173                long npages, unsigned long uaddr,
0174                enum dma_data_direction direction,
0175                unsigned long attrs)
0176 {
0177     unsigned int *dp, *orig_dp;
0178     unsigned int rpn;
0179     long l;
0180
0181     DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
0182
0183     orig_dp = dp = ((unsigned int*)tbl->it_base) + index;
0184
0185     /* On U3, all memory is contiguous, so we can move this
0186      * out of the loop.
0187      */
0188     l = npages;
0189     while (l--) {
0190         rpn = __pa(uaddr) >> DART_PAGE_SHIFT;
0191
0192         *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
0193
0194         uaddr += DART_PAGE_SIZE;
0195     }
0196     dart_cache_sync(orig_dp, npages);
0197
0198     if (dart_is_u4) {
0199         rpn = index;
0200         while (npages--)
0201             dart_tlb_invalidate_one(rpn++);
0202     } else {
0203         dart_dirty = 1;
0204     }
0205     return 0;
0206 }
0207
0208
0209 static void dart_free(struct iommu_table *tbl, long index, long npages)
0210 {
0211     unsigned int *dp, *orig_dp;
0212     long orig_npages = npages;
0213
0214     /* We don't worry about flushing the TLB cache. The only drawback of
0215      * not doing it is that we won't catch buggy device drivers doing
0216      * bad DMAs, but then no 32-bit architecture ever does either.
0217      */
0218
0219     DBG("dart: free at: %lx, %lx\n", index, npages);
0220
0221     orig_dp = dp  = ((unsigned int *)tbl->it_base) + index;
0222
0223     while (npages--)
0224         *(dp++) = dart_emptyval;
0225
0226     dart_cache_sync(orig_dp, orig_npages);
0227 }
0228
0229 static void __init allocate_dart(void)
0230 {
0231     unsigned long tmp;
0232
0233     /* 512 pages (2MB) is max DART tablesize. */
0234     dart_tablesize = 1UL << 21;
0235
0236     /*
0237      * 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
0238      * will blow up an entire large page anyway in the kernel mapping.
0239      */
0240     dart_tablebase = memblock_alloc_try_nid_raw(SZ_16M, SZ_16M,
0241                     MEMBLOCK_LOW_LIMIT, SZ_2G,
0242                     NUMA_NO_NODE);
0243     if (!dart_tablebase)
0244         panic("Failed to allocate 16MB below 2GB for DART table\n");
0245
0246     /* There is no point scanning the DART space for leaks*/
0247     kmemleak_no_scan((void *)dart_tablebase);
0248
0249     /* Allocate a spare page to map all invalid DART pages. We need to do
0250      * that to work around what looks like a problem with the HT bridge
0251      * prefetching into invalid pages and corrupting data
0252      */
0253     tmp = memblock_phys_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
0254     if (!tmp)
0255         panic("DART: table allocation failed\n");
0256
0257     dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) &
0258                      DARTMAP_RPNMASK);
0259
0260     printk(KERN_INFO "DART table allocated at: %p\n", dart_tablebase);
0261 }
0262
0263 static int __init dart_init(struct device_node *dart_node)
0264 {
0265     unsigned int i;
0266     unsigned long base, size;
0267     struct resource r;
0268
0269     /* IOMMU disabled by the user ? bail out */
0270     if (iommu_is_off)
0271         return -ENODEV;
0272
0273     /*
0274      * Only use the DART if the machine has more than 1GB of RAM
0275      * or if requested with iommu=on on cmdline.
0276      *
0277      * 1GB of RAM is picked as limit because some default devices
0278      * (i.e. Airport Extreme) have 30 bit address range limits.
0279      */
0280
0281     if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull)
0282         return -ENODEV;
0283
0284     /* Get DART registers */
0285     if (of_address_to_resource(dart_node, 0, &r))
0286         panic("DART: can't get register base ! ");
0287
0288     /* Map in DART registers */
0289     dart = ioremap(r.start, resource_size(&r));
0290     if (dart == NULL)
0291         panic("DART: Cannot map registers!");
0292
0293     /* Allocate the DART and dummy page */
0294     allocate_dart();
0295
0296     /* Fill initial table */
0297     for (i = 0; i < dart_tablesize/4; i++)
0298         dart_tablebase[i] = dart_emptyval;
0299
0300     /* Push to memory */
0301     dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32));
0302
0303     /* Initialize DART with table base and enable it. */
0304     base = ((unsigned long)dart_tablebase) >> DART_PAGE_SHIFT;
0305     size = dart_tablesize >> DART_PAGE_SHIFT;
0306     if (dart_is_u4) {
0307         size &= DART_SIZE_U4_SIZE_MASK;
0308         DART_OUT(DART_BASE_U4, base);
0309         DART_OUT(DART_SIZE_U4, size);
0310         DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE);
0311     } else {
0312         size &= DART_CNTL_U3_SIZE_MASK;
0313         DART_OUT(DART_CNTL,
0314              DART_CNTL_U3_ENABLE |
0315              (base << DART_CNTL_U3_BASE_SHIFT) |
0316              (size << DART_CNTL_U3_SIZE_SHIFT));
0317     }
0318
0319     /* Invalidate DART to get rid of possible stale TLBs */
0320     dart_tlb_invalidate_all();
0321
0322     printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n",
0323            dart_is_u4 ? "U4" : "U3");
0324
0325     return 0;
0326 }
0327
0328 static struct iommu_table_ops iommu_dart_ops = {
0329     .set = dart_build,
0330     .clear = dart_free,
0331     .flush = dart_flush,
0332 };
0333
0334 static void iommu_table_dart_setup(void)
0335 {
0336     iommu_table_dart.it_busno = 0;
0337     iommu_table_dart.it_offset = 0;
0338     /* it_size is in number of entries */
0339     iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
0340     iommu_table_dart.it_page_shift = IOMMU_PAGE_SHIFT_4K;
0341
0342     /* Initialize the common IOMMU code */
0343     iommu_table_dart.it_base = (unsigned long)dart_tablebase;
0344     iommu_table_dart.it_index = 0;
0345     iommu_table_dart.it_blocksize = 1;
0346     iommu_table_dart.it_ops = &iommu_dart_ops;
0347     if (!iommu_init_table(&iommu_table_dart, -1, 0, 0))
0348         panic("Failed to initialize iommu table");
0349
0350     /* Reserve the last page of the DART to avoid possible prefetch
0351      * past the DART mapped area
0352      */
0353     set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
0354 }
0355
0356 static void pci_dma_bus_setup_dart(struct pci_bus *bus)
0357 {
0358     if (!iommu_table_dart_inited) {
0359         iommu_table_dart_inited = 1;
0360         iommu_table_dart_setup();
0361     }
0362 }
0363
0364 static bool dart_device_on_pcie(struct device *dev)
0365 {
0366     struct device_node *np = of_node_get(dev->of_node);
0367
0368     while(np) {
0369         if (of_device_is_compatible(np, "U4-pcie") ||
0370             of_device_is_compatible(np, "u4-pcie")) {
0371             of_node_put(np);
0372             return true;
0373         }
0374         np = of_get_next_parent(np);
0375     }
0376     return false;
0377 }
0378
0379 static void pci_dma_dev_setup_dart(struct pci_dev *dev)
0380 {
0381     if (dart_is_u4 && dart_device_on_pcie(&dev->dev))
0382         dev->dev.archdata.dma_offset = DART_U4_BYPASS_BASE;
0383     set_iommu_table_base(&dev->dev, &iommu_table_dart);
0384 }
0385
0386 static bool iommu_bypass_supported_dart(struct pci_dev *dev, u64 mask)
0387 {
0388     return dart_is_u4 &&
0389         dart_device_on_pcie(&dev->dev) &&
0390         mask >= DMA_BIT_MASK(40);
0391 }
0392
0393 void __init iommu_init_early_dart(struct pci_controller_ops *controller_ops)
0394 {
0395     struct device_node *dn;
0396
0397     /* Find the DART in the device-tree */
0398     dn = of_find_compatible_node(NULL, "dart", "u3-dart");
0399     if (dn == NULL) {
0400         dn = of_find_compatible_node(NULL, "dart", "u4-dart");
0401         if (dn == NULL)
0402             return; /* use default direct_dma_ops */
0403         dart_is_u4 = 1;
0404     }
0405
0406     /* Initialize the DART HW */
0407     if (dart_init(dn) != 0) {
0408         of_node_put(dn);
0409         return;
0410     }
0411     /*
0412      * U4 supports a DART bypass, we use it for 64-bit capable devices to
0413      * improve performance.  However, that only works for devices connected
0414      * to the U4 own PCIe interface, not bridged through hypertransport.
0415      * We need the device to support at least 40 bits of addresses.
0416      */
0417     controller_ops->dma_dev_setup = pci_dma_dev_setup_dart;
0418     controller_ops->dma_bus_setup = pci_dma_bus_setup_dart;
0419     controller_ops->iommu_bypass_supported = iommu_bypass_supported_dart;
0420
0421     /* Setup pci_dma ops */
0422     set_pci_dma_ops(&dma_iommu_ops);
0423     of_node_put(dn);
0424 }
0425
0426 #ifdef CONFIG_PM
0427 static void iommu_dart_restore(void)
0428 {
0429     dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32));
0430     dart_tlb_invalidate_all();
0431 }
0432
0433 static int __init iommu_init_late_dart(void)
0434 {
0435     if (!dart_tablebase)
0436         return 0;
0437
0438     ppc_md.iommu_restore = iommu_dart_restore;
0439
0440     return 0;
0441 }
0442
0443 late_initcall(iommu_init_late_dart);
0444 #endif /* CONFIG_PM */