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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  64-bit pSeries and RS/6000 setup code.
0004  *
0005  *  Copyright (C) 1995  Linus Torvalds
0006  *  Adapted from 'alpha' version by Gary Thomas
0007  *  Modified by Cort Dougan (cort@cs.nmt.edu)
0008  *  Modified by PPC64 Team, IBM Corp
0009  */
0010 
0011 /*
0012  * bootup setup stuff..
0013  */
0014 
0015 #include <linux/cpu.h>
0016 #include <linux/errno.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/sched.h>
0019 #include <linux/kernel.h>
0020 #include <linux/mm.h>
0021 #include <linux/stddef.h>
0022 #include <linux/unistd.h>
0023 #include <linux/user.h>
0024 #include <linux/tty.h>
0025 #include <linux/major.h>
0026 #include <linux/interrupt.h>
0027 #include <linux/reboot.h>
0028 #include <linux/init.h>
0029 #include <linux/ioport.h>
0030 #include <linux/console.h>
0031 #include <linux/pci.h>
0032 #include <linux/utsname.h>
0033 #include <linux/adb.h>
0034 #include <linux/export.h>
0035 #include <linux/delay.h>
0036 #include <linux/irq.h>
0037 #include <linux/seq_file.h>
0038 #include <linux/root_dev.h>
0039 #include <linux/of.h>
0040 #include <linux/of_irq.h>
0041 #include <linux/of_pci.h>
0042 #include <linux/memblock.h>
0043 #include <linux/swiotlb.h>
0044 
0045 #include <asm/mmu.h>
0046 #include <asm/processor.h>
0047 #include <asm/io.h>
0048 #include <asm/rtas.h>
0049 #include <asm/pci-bridge.h>
0050 #include <asm/iommu.h>
0051 #include <asm/dma.h>
0052 #include <asm/machdep.h>
0053 #include <asm/irq.h>
0054 #include <asm/time.h>
0055 #include <asm/nvram.h>
0056 #include <asm/pmc.h>
0057 #include <asm/xics.h>
0058 #include <asm/xive.h>
0059 #include <asm/ppc-pci.h>
0060 #include <asm/i8259.h>
0061 #include <asm/udbg.h>
0062 #include <asm/smp.h>
0063 #include <asm/firmware.h>
0064 #include <asm/eeh.h>
0065 #include <asm/reg.h>
0066 #include <asm/plpar_wrappers.h>
0067 #include <asm/kexec.h>
0068 #include <asm/isa-bridge.h>
0069 #include <asm/security_features.h>
0070 #include <asm/asm-const.h>
0071 #include <asm/idle.h>
0072 #include <asm/swiotlb.h>
0073 #include <asm/svm.h>
0074 #include <asm/dtl.h>
0075 #include <asm/hvconsole.h>
0076 #include <asm/setup.h>
0077 
0078 #include "pseries.h"
0079 
0080 DEFINE_STATIC_KEY_FALSE(shared_processor);
0081 EXPORT_SYMBOL(shared_processor);
0082 
0083 int CMO_PrPSP = -1;
0084 int CMO_SecPSP = -1;
0085 unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K);
0086 EXPORT_SYMBOL(CMO_PageSize);
0087 
0088 int fwnmi_active;  /* TRUE if an FWNMI handler is present */
0089 int ibm_nmi_interlock_token;
0090 u32 pseries_security_flavor;
0091 
0092 static void pSeries_show_cpuinfo(struct seq_file *m)
0093 {
0094     struct device_node *root;
0095     const char *model = "";
0096 
0097     root = of_find_node_by_path("/");
0098     if (root)
0099         model = of_get_property(root, "model", NULL);
0100     seq_printf(m, "machine\t\t: CHRP %s\n", model);
0101     of_node_put(root);
0102     if (radix_enabled())
0103         seq_printf(m, "MMU\t\t: Radix\n");
0104     else
0105         seq_printf(m, "MMU\t\t: Hash\n");
0106 }
0107 
0108 /* Initialize firmware assisted non-maskable interrupts if
0109  * the firmware supports this feature.
0110  */
0111 static void __init fwnmi_init(void)
0112 {
0113     unsigned long system_reset_addr, machine_check_addr;
0114     u8 *mce_data_buf;
0115     unsigned int i;
0116     int nr_cpus = num_possible_cpus();
0117 #ifdef CONFIG_PPC_64S_HASH_MMU
0118     struct slb_entry *slb_ptr;
0119     size_t size;
0120 #endif
0121     int ibm_nmi_register_token;
0122 
0123     ibm_nmi_register_token = rtas_token("ibm,nmi-register");
0124     if (ibm_nmi_register_token == RTAS_UNKNOWN_SERVICE)
0125         return;
0126 
0127     ibm_nmi_interlock_token = rtas_token("ibm,nmi-interlock");
0128     if (WARN_ON(ibm_nmi_interlock_token == RTAS_UNKNOWN_SERVICE))
0129         return;
0130 
0131     /* If the kernel's not linked at zero we point the firmware at low
0132      * addresses anyway, and use a trampoline to get to the real code. */
0133     system_reset_addr  = __pa(system_reset_fwnmi) - PHYSICAL_START;
0134     machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START;
0135 
0136     if (0 == rtas_call(ibm_nmi_register_token, 2, 1, NULL,
0137                system_reset_addr, machine_check_addr))
0138         fwnmi_active = 1;
0139 
0140     /*
0141      * Allocate a chunk for per cpu buffer to hold rtas errorlog.
0142      * It will be used in real mode mce handler, hence it needs to be
0143      * below RMA.
0144      */
0145     mce_data_buf = memblock_alloc_try_nid_raw(RTAS_ERROR_LOG_MAX * nr_cpus,
0146                     RTAS_ERROR_LOG_MAX, MEMBLOCK_LOW_LIMIT,
0147                     ppc64_rma_size, NUMA_NO_NODE);
0148     if (!mce_data_buf)
0149         panic("Failed to allocate %d bytes below %pa for MCE buffer\n",
0150               RTAS_ERROR_LOG_MAX * nr_cpus, &ppc64_rma_size);
0151 
0152     for_each_possible_cpu(i) {
0153         paca_ptrs[i]->mce_data_buf = mce_data_buf +
0154                         (RTAS_ERROR_LOG_MAX * i);
0155     }
0156 
0157 #ifdef CONFIG_PPC_64S_HASH_MMU
0158     if (!radix_enabled()) {
0159         /* Allocate per cpu area to save old slb contents during MCE */
0160         size = sizeof(struct slb_entry) * mmu_slb_size * nr_cpus;
0161         slb_ptr = memblock_alloc_try_nid_raw(size,
0162                 sizeof(struct slb_entry), MEMBLOCK_LOW_LIMIT,
0163                 ppc64_rma_size, NUMA_NO_NODE);
0164         if (!slb_ptr)
0165             panic("Failed to allocate %zu bytes below %pa for slb area\n",
0166                   size, &ppc64_rma_size);
0167 
0168         for_each_possible_cpu(i)
0169             paca_ptrs[i]->mce_faulty_slbs = slb_ptr + (mmu_slb_size * i);
0170     }
0171 #endif
0172 }
0173 
0174 /*
0175  * Affix a device for the first timer to the platform bus if
0176  * we have firmware support for the H_WATCHDOG hypercall.
0177  */
0178 static __init int pseries_wdt_init(void)
0179 {
0180     if (firmware_has_feature(FW_FEATURE_WATCHDOG))
0181         platform_device_register_simple("pseries-wdt", 0, NULL, 0);
0182     return 0;
0183 }
0184 machine_subsys_initcall(pseries, pseries_wdt_init);
0185 
0186 static void pseries_8259_cascade(struct irq_desc *desc)
0187 {
0188     struct irq_chip *chip = irq_desc_get_chip(desc);
0189     unsigned int cascade_irq = i8259_irq();
0190 
0191     if (cascade_irq)
0192         generic_handle_irq(cascade_irq);
0193 
0194     chip->irq_eoi(&desc->irq_data);
0195 }
0196 
0197 static void __init pseries_setup_i8259_cascade(void)
0198 {
0199     struct device_node *np, *old, *found = NULL;
0200     unsigned int cascade;
0201     const u32 *addrp;
0202     unsigned long intack = 0;
0203     int naddr;
0204 
0205     for_each_node_by_type(np, "interrupt-controller") {
0206         if (of_device_is_compatible(np, "chrp,iic")) {
0207             found = np;
0208             break;
0209         }
0210     }
0211 
0212     if (found == NULL) {
0213         printk(KERN_DEBUG "pic: no ISA interrupt controller\n");
0214         return;
0215     }
0216 
0217     cascade = irq_of_parse_and_map(found, 0);
0218     if (!cascade) {
0219         printk(KERN_ERR "pic: failed to map cascade interrupt");
0220         return;
0221     }
0222     pr_debug("pic: cascade mapped to irq %d\n", cascade);
0223 
0224     for (old = of_node_get(found); old != NULL ; old = np) {
0225         np = of_get_parent(old);
0226         of_node_put(old);
0227         if (np == NULL)
0228             break;
0229         if (!of_node_name_eq(np, "pci"))
0230             continue;
0231         addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
0232         if (addrp == NULL)
0233             continue;
0234         naddr = of_n_addr_cells(np);
0235         intack = addrp[naddr-1];
0236         if (naddr > 1)
0237             intack |= ((unsigned long)addrp[naddr-2]) << 32;
0238     }
0239     if (intack)
0240         printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
0241     i8259_init(found, intack);
0242     of_node_put(found);
0243     irq_set_chained_handler(cascade, pseries_8259_cascade);
0244 }
0245 
0246 static void __init pseries_init_irq(void)
0247 {
0248     /* Try using a XIVE if available, otherwise use a XICS */
0249     if (!xive_spapr_init()) {
0250         xics_init();
0251         pseries_setup_i8259_cascade();
0252     }
0253 }
0254 
0255 static void pseries_lpar_enable_pmcs(void)
0256 {
0257     unsigned long set, reset;
0258 
0259     set = 1UL << 63;
0260     reset = 0;
0261     plpar_hcall_norets(H_PERFMON, set, reset);
0262 }
0263 
0264 static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
0265 {
0266     struct of_reconfig_data *rd = data;
0267     struct device_node *parent, *np = rd->dn;
0268     struct pci_dn *pdn;
0269     int err = NOTIFY_OK;
0270 
0271     switch (action) {
0272     case OF_RECONFIG_ATTACH_NODE:
0273         parent = of_get_parent(np);
0274         pdn = parent ? PCI_DN(parent) : NULL;
0275         if (pdn)
0276             pci_add_device_node_info(pdn->phb, np);
0277 
0278         of_node_put(parent);
0279         break;
0280     case OF_RECONFIG_DETACH_NODE:
0281         pdn = PCI_DN(np);
0282         if (pdn)
0283             list_del(&pdn->list);
0284         break;
0285     default:
0286         err = NOTIFY_DONE;
0287         break;
0288     }
0289     return err;
0290 }
0291 
0292 static struct notifier_block pci_dn_reconfig_nb = {
0293     .notifier_call = pci_dn_reconfig_notifier,
0294 };
0295 
0296 struct kmem_cache *dtl_cache;
0297 
0298 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
0299 /*
0300  * Allocate space for the dispatch trace log for all possible cpus
0301  * and register the buffers with the hypervisor.  This is used for
0302  * computing time stolen by the hypervisor.
0303  */
0304 static int alloc_dispatch_logs(void)
0305 {
0306     if (!firmware_has_feature(FW_FEATURE_SPLPAR))
0307         return 0;
0308 
0309     if (!dtl_cache)
0310         return 0;
0311 
0312     alloc_dtl_buffers(0);
0313 
0314     /* Register the DTL for the current (boot) cpu */
0315     register_dtl_buffer(smp_processor_id());
0316 
0317     return 0;
0318 }
0319 #else /* !CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
0320 static inline int alloc_dispatch_logs(void)
0321 {
0322     return 0;
0323 }
0324 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
0325 
0326 static int alloc_dispatch_log_kmem_cache(void)
0327 {
0328     void (*ctor)(void *) = get_dtl_cache_ctor();
0329 
0330     dtl_cache = kmem_cache_create("dtl", DISPATCH_LOG_BYTES,
0331                         DISPATCH_LOG_BYTES, 0, ctor);
0332     if (!dtl_cache) {
0333         pr_warn("Failed to create dispatch trace log buffer cache\n");
0334         pr_warn("Stolen time statistics will be unreliable\n");
0335         return 0;
0336     }
0337 
0338     return alloc_dispatch_logs();
0339 }
0340 machine_early_initcall(pseries, alloc_dispatch_log_kmem_cache);
0341 
0342 DEFINE_PER_CPU(u64, idle_spurr_cycles);
0343 DEFINE_PER_CPU(u64, idle_entry_purr_snap);
0344 DEFINE_PER_CPU(u64, idle_entry_spurr_snap);
0345 static void pseries_lpar_idle(void)
0346 {
0347     /*
0348      * Default handler to go into low thread priority and possibly
0349      * low power mode by ceding processor to hypervisor
0350      */
0351 
0352     if (!prep_irq_for_idle())
0353         return;
0354 
0355     /* Indicate to hypervisor that we are idle. */
0356     pseries_idle_prolog();
0357 
0358     /*
0359      * Yield the processor to the hypervisor.  We return if
0360      * an external interrupt occurs (which are driven prior
0361      * to returning here) or if a prod occurs from another
0362      * processor. When returning here, external interrupts
0363      * are enabled.
0364      */
0365     cede_processor();
0366 
0367     pseries_idle_epilog();
0368 }
0369 
0370 static bool pseries_reloc_on_exception_enabled;
0371 
0372 bool pseries_reloc_on_exception(void)
0373 {
0374     return pseries_reloc_on_exception_enabled;
0375 }
0376 EXPORT_SYMBOL_GPL(pseries_reloc_on_exception);
0377 
0378 /*
0379  * Enable relocation on during exceptions. This has partition wide scope and
0380  * may take a while to complete, if it takes longer than one second we will
0381  * just give up rather than wasting any more time on this - if that turns out
0382  * to ever be a problem in practice we can move this into a kernel thread to
0383  * finish off the process later in boot.
0384  */
0385 bool pseries_enable_reloc_on_exc(void)
0386 {
0387     long rc;
0388     unsigned int delay, total_delay = 0;
0389 
0390     while (1) {
0391         rc = enable_reloc_on_exceptions();
0392         if (!H_IS_LONG_BUSY(rc)) {
0393             if (rc == H_P2) {
0394                 pr_info("Relocation on exceptions not"
0395                     " supported\n");
0396                 return false;
0397             } else if (rc != H_SUCCESS) {
0398                 pr_warn("Unable to enable relocation"
0399                     " on exceptions: %ld\n", rc);
0400                 return false;
0401             }
0402             pseries_reloc_on_exception_enabled = true;
0403             return true;
0404         }
0405 
0406         delay = get_longbusy_msecs(rc);
0407         total_delay += delay;
0408         if (total_delay > 1000) {
0409             pr_warn("Warning: Giving up waiting to enable "
0410                 "relocation on exceptions (%u msec)!\n",
0411                 total_delay);
0412             return false;
0413         }
0414 
0415         mdelay(delay);
0416     }
0417 }
0418 EXPORT_SYMBOL(pseries_enable_reloc_on_exc);
0419 
0420 void pseries_disable_reloc_on_exc(void)
0421 {
0422     long rc;
0423 
0424     while (1) {
0425         rc = disable_reloc_on_exceptions();
0426         if (!H_IS_LONG_BUSY(rc))
0427             break;
0428         mdelay(get_longbusy_msecs(rc));
0429     }
0430     if (rc == H_SUCCESS)
0431         pseries_reloc_on_exception_enabled = false;
0432     else
0433         pr_warn("Warning: Failed to disable relocation on exceptions: %ld\n",
0434             rc);
0435 }
0436 EXPORT_SYMBOL(pseries_disable_reloc_on_exc);
0437 
0438 #ifdef __LITTLE_ENDIAN__
0439 void pseries_big_endian_exceptions(void)
0440 {
0441     long rc;
0442 
0443     while (1) {
0444         rc = enable_big_endian_exceptions();
0445         if (!H_IS_LONG_BUSY(rc))
0446             break;
0447         mdelay(get_longbusy_msecs(rc));
0448     }
0449 
0450     /*
0451      * At this point it is unlikely panic() will get anything
0452      * out to the user, since this is called very late in kexec
0453      * but at least this will stop us from continuing on further
0454      * and creating an even more difficult to debug situation.
0455      *
0456      * There is a known problem when kdump'ing, if cpus are offline
0457      * the above call will fail. Rather than panicking again, keep
0458      * going and hope the kdump kernel is also little endian, which
0459      * it usually is.
0460      */
0461     if (rc && !kdump_in_progress())
0462         panic("Could not enable big endian exceptions");
0463 }
0464 
0465 void __init pseries_little_endian_exceptions(void)
0466 {
0467     long rc;
0468 
0469     while (1) {
0470         rc = enable_little_endian_exceptions();
0471         if (!H_IS_LONG_BUSY(rc))
0472             break;
0473         mdelay(get_longbusy_msecs(rc));
0474     }
0475     if (rc) {
0476         ppc_md.progress("H_SET_MODE LE exception fail", 0);
0477         panic("Could not enable little endian exceptions");
0478     }
0479 }
0480 #endif
0481 
0482 static void __init pSeries_discover_phbs(void)
0483 {
0484     struct device_node *node;
0485     struct pci_controller *phb;
0486     struct device_node *root = of_find_node_by_path("/");
0487 
0488     for_each_child_of_node(root, node) {
0489         if (!of_node_is_type(node, "pci") &&
0490             !of_node_is_type(node, "pciex"))
0491             continue;
0492 
0493         phb = pcibios_alloc_controller(node);
0494         if (!phb)
0495             continue;
0496         rtas_setup_phb(phb);
0497         pci_process_bridge_OF_ranges(phb, node, 0);
0498         isa_bridge_find_early(phb);
0499         phb->controller_ops = pseries_pci_controller_ops;
0500 
0501         /* create pci_dn's for DT nodes under this PHB */
0502         pci_devs_phb_init_dynamic(phb);
0503 
0504         pseries_msi_allocate_domains(phb);
0505     }
0506 
0507     of_node_put(root);
0508 
0509     /*
0510      * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
0511      * in chosen.
0512      */
0513     of_pci_check_probe_only();
0514 }
0515 
0516 static void init_cpu_char_feature_flags(struct h_cpu_char_result *result)
0517 {
0518     /*
0519      * The features below are disabled by default, so we instead look to see
0520      * if firmware has *enabled* them, and set them if so.
0521      */
0522     if (result->character & H_CPU_CHAR_SPEC_BAR_ORI31)
0523         security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
0524 
0525     if (result->character & H_CPU_CHAR_BCCTRL_SERIALISED)
0526         security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
0527 
0528     if (result->character & H_CPU_CHAR_L1D_FLUSH_ORI30)
0529         security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
0530 
0531     if (result->character & H_CPU_CHAR_L1D_FLUSH_TRIG2)
0532         security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
0533 
0534     if (result->character & H_CPU_CHAR_L1D_THREAD_PRIV)
0535         security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
0536 
0537     if (result->character & H_CPU_CHAR_COUNT_CACHE_DISABLED)
0538         security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
0539 
0540     if (result->character & H_CPU_CHAR_BCCTR_FLUSH_ASSIST)
0541         security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
0542 
0543     if (result->character & H_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST)
0544         security_ftr_set(SEC_FTR_BCCTR_LINK_FLUSH_ASSIST);
0545 
0546     if (result->behaviour & H_CPU_BEHAV_FLUSH_COUNT_CACHE)
0547         security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
0548 
0549     if (result->behaviour & H_CPU_BEHAV_FLUSH_LINK_STACK)
0550         security_ftr_set(SEC_FTR_FLUSH_LINK_STACK);
0551 
0552     /*
0553      * The features below are enabled by default, so we instead look to see
0554      * if firmware has *disabled* them, and clear them if so.
0555      * H_CPU_BEHAV_FAVOUR_SECURITY_H could be set only if
0556      * H_CPU_BEHAV_FAVOUR_SECURITY is.
0557      */
0558     if (!(result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY)) {
0559         security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
0560         pseries_security_flavor = 0;
0561     } else if (result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY_H)
0562         pseries_security_flavor = 1;
0563     else
0564         pseries_security_flavor = 2;
0565 
0566     if (!(result->behaviour & H_CPU_BEHAV_L1D_FLUSH_PR))
0567         security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
0568 
0569     if (result->behaviour & H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY)
0570         security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
0571 
0572     if (result->behaviour & H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS)
0573         security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
0574 
0575     if (result->behaviour & H_CPU_BEHAV_NO_STF_BARRIER)
0576         security_ftr_clear(SEC_FTR_STF_BARRIER);
0577 
0578     if (!(result->behaviour & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR))
0579         security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
0580 }
0581 
0582 void pseries_setup_security_mitigations(void)
0583 {
0584     struct h_cpu_char_result result;
0585     enum l1d_flush_type types;
0586     bool enable;
0587     long rc;
0588 
0589     /*
0590      * Set features to the defaults assumed by init_cpu_char_feature_flags()
0591      * so it can set/clear again any features that might have changed after
0592      * migration, and in case the hypercall fails and it is not even called.
0593      */
0594     powerpc_security_features = SEC_FTR_DEFAULT;
0595 
0596     rc = plpar_get_cpu_characteristics(&result);
0597     if (rc == H_SUCCESS)
0598         init_cpu_char_feature_flags(&result);
0599 
0600     /*
0601      * We're the guest so this doesn't apply to us, clear it to simplify
0602      * handling of it elsewhere.
0603      */
0604     security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
0605 
0606     types = L1D_FLUSH_FALLBACK;
0607 
0608     if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
0609         types |= L1D_FLUSH_MTTRIG;
0610 
0611     if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
0612         types |= L1D_FLUSH_ORI;
0613 
0614     enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
0615          security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR);
0616 
0617     setup_rfi_flush(types, enable);
0618     setup_count_cache_flush();
0619 
0620     enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
0621          security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
0622     setup_entry_flush(enable);
0623 
0624     enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
0625          security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
0626     setup_uaccess_flush(enable);
0627 
0628     setup_stf_barrier();
0629 }
0630 
0631 #ifdef CONFIG_PCI_IOV
0632 enum rtas_iov_fw_value_map {
0633     NUM_RES_PROPERTY  = 0, /* Number of Resources */
0634     LOW_INT           = 1, /* Lowest 32 bits of Address */
0635     START_OF_ENTRIES  = 2, /* Always start of entry */
0636     APERTURE_PROPERTY = 2, /* Start of entry+ to  Aperture Size */
0637     WDW_SIZE_PROPERTY = 4, /* Start of entry+ to Window Size */
0638     NEXT_ENTRY        = 7  /* Go to next entry on array */
0639 };
0640 
0641 enum get_iov_fw_value_index {
0642     BAR_ADDRS     = 1,    /*  Get Bar Address */
0643     APERTURE_SIZE = 2,    /*  Get Aperture Size */
0644     WDW_SIZE      = 3     /*  Get Window Size */
0645 };
0646 
0647 static resource_size_t pseries_get_iov_fw_value(struct pci_dev *dev, int resno,
0648                         enum get_iov_fw_value_index value)
0649 {
0650     const int *indexes;
0651     struct device_node *dn = pci_device_to_OF_node(dev);
0652     int i, num_res, ret = 0;
0653 
0654     indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
0655     if (!indexes)
0656         return  0;
0657 
0658     /*
0659      * First element in the array is the number of Bars
0660      * returned.  Search through the list to find the matching
0661      * bar
0662      */
0663     num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
0664     if (resno >= num_res)
0665         return 0; /* or an error */
0666 
0667     i = START_OF_ENTRIES + NEXT_ENTRY * resno;
0668     switch (value) {
0669     case BAR_ADDRS:
0670         ret = of_read_number(&indexes[i], 2);
0671         break;
0672     case APERTURE_SIZE:
0673         ret = of_read_number(&indexes[i + APERTURE_PROPERTY], 2);
0674         break;
0675     case WDW_SIZE:
0676         ret = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2);
0677         break;
0678     }
0679 
0680     return ret;
0681 }
0682 
0683 static void of_pci_set_vf_bar_size(struct pci_dev *dev, const int *indexes)
0684 {
0685     struct resource *res;
0686     resource_size_t base, size;
0687     int i, r, num_res;
0688 
0689     num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
0690     num_res = min_t(int, num_res, PCI_SRIOV_NUM_BARS);
0691     for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS;
0692          i += NEXT_ENTRY, r++) {
0693         res = &dev->resource[r + PCI_IOV_RESOURCES];
0694         base = of_read_number(&indexes[i], 2);
0695         size = of_read_number(&indexes[i + APERTURE_PROPERTY], 2);
0696         res->flags = pci_parse_of_flags(of_read_number
0697                         (&indexes[i + LOW_INT], 1), 0);
0698         res->flags |= (IORESOURCE_MEM_64 | IORESOURCE_PCI_FIXED);
0699         res->name = pci_name(dev);
0700         res->start = base;
0701         res->end = base + size - 1;
0702     }
0703 }
0704 
0705 static void of_pci_parse_iov_addrs(struct pci_dev *dev, const int *indexes)
0706 {
0707     struct resource *res, *root, *conflict;
0708     resource_size_t base, size;
0709     int i, r, num_res;
0710 
0711     /*
0712      * First element in the array is the number of Bars
0713      * returned.  Search through the list to find the matching
0714      * bars assign them from firmware into resources structure.
0715      */
0716     num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
0717     for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS;
0718          i += NEXT_ENTRY, r++) {
0719         res = &dev->resource[r + PCI_IOV_RESOURCES];
0720         base = of_read_number(&indexes[i], 2);
0721         size = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2);
0722         res->name = pci_name(dev);
0723         res->start = base;
0724         res->end = base + size - 1;
0725         root = &iomem_resource;
0726         dev_dbg(&dev->dev,
0727             "pSeries IOV BAR %d: trying firmware assignment %pR\n",
0728              r + PCI_IOV_RESOURCES, res);
0729         conflict = request_resource_conflict(root, res);
0730         if (conflict) {
0731             dev_info(&dev->dev,
0732                  "BAR %d: %pR conflicts with %s %pR\n",
0733                  r + PCI_IOV_RESOURCES, res,
0734                  conflict->name, conflict);
0735             res->flags |= IORESOURCE_UNSET;
0736         }
0737     }
0738 }
0739 
0740 static void pseries_disable_sriov_resources(struct pci_dev *pdev)
0741 {
0742     int i;
0743 
0744     pci_warn(pdev, "No hypervisor support for SR-IOV on this device, IOV BARs disabled.\n");
0745     for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
0746         pdev->resource[i + PCI_IOV_RESOURCES].flags = 0;
0747 }
0748 
0749 static void pseries_pci_fixup_resources(struct pci_dev *pdev)
0750 {
0751     const int *indexes;
0752     struct device_node *dn = pci_device_to_OF_node(pdev);
0753 
0754     /*Firmware must support open sriov otherwise dont configure*/
0755     indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
0756     if (indexes)
0757         of_pci_set_vf_bar_size(pdev, indexes);
0758     else
0759         pseries_disable_sriov_resources(pdev);
0760 }
0761 
0762 static void pseries_pci_fixup_iov_resources(struct pci_dev *pdev)
0763 {
0764     const int *indexes;
0765     struct device_node *dn = pci_device_to_OF_node(pdev);
0766 
0767     if (!pdev->is_physfn)
0768         return;
0769     /*Firmware must support open sriov otherwise don't configure*/
0770     indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
0771     if (indexes)
0772         of_pci_parse_iov_addrs(pdev, indexes);
0773     else
0774         pseries_disable_sriov_resources(pdev);
0775 }
0776 
0777 static resource_size_t pseries_pci_iov_resource_alignment(struct pci_dev *pdev,
0778                               int resno)
0779 {
0780     const __be32 *reg;
0781     struct device_node *dn = pci_device_to_OF_node(pdev);
0782 
0783     /*Firmware must support open sriov otherwise report regular alignment*/
0784     reg = of_get_property(dn, "ibm,is-open-sriov-pf", NULL);
0785     if (!reg)
0786         return pci_iov_resource_size(pdev, resno);
0787 
0788     if (!pdev->is_physfn)
0789         return 0;
0790     return pseries_get_iov_fw_value(pdev,
0791                     resno - PCI_IOV_RESOURCES,
0792                     APERTURE_SIZE);
0793 }
0794 #endif
0795 
0796 static void __init pSeries_setup_arch(void)
0797 {
0798     set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
0799 
0800     /* Discover PIC type and setup ppc_md accordingly */
0801     smp_init_pseries();
0802 
0803 
0804     if (radix_enabled() && !mmu_has_feature(MMU_FTR_GTSE))
0805         if (!firmware_has_feature(FW_FEATURE_RPT_INVALIDATE))
0806             panic("BUG: Radix support requires either GTSE or RPT_INVALIDATE\n");
0807 
0808 
0809     /* openpic global configuration register (64-bit format). */
0810     /* openpic Interrupt Source Unit pointer (64-bit format). */
0811     /* python0 facility area (mmio) (64-bit format) REAL address. */
0812 
0813     /* init to some ~sane value until calibrate_delay() runs */
0814     loops_per_jiffy = 50000000;
0815 
0816     fwnmi_init();
0817 
0818     pseries_setup_security_mitigations();
0819     if (!radix_enabled())
0820         pseries_lpar_read_hblkrm_characteristics();
0821 
0822     /* By default, only probe PCI (can be overridden by rtas_pci) */
0823     pci_add_flags(PCI_PROBE_ONLY);
0824 
0825     /* Find and initialize PCI host bridges */
0826     init_pci_config_tokens();
0827     of_reconfig_notifier_register(&pci_dn_reconfig_nb);
0828 
0829     pSeries_nvram_init();
0830 
0831     if (firmware_has_feature(FW_FEATURE_LPAR)) {
0832         vpa_init(boot_cpuid);
0833 
0834         if (lppaca_shared_proc(get_lppaca())) {
0835             static_branch_enable(&shared_processor);
0836             pv_spinlocks_init();
0837         }
0838 
0839         ppc_md.power_save = pseries_lpar_idle;
0840         ppc_md.enable_pmcs = pseries_lpar_enable_pmcs;
0841 #ifdef CONFIG_PCI_IOV
0842         ppc_md.pcibios_fixup_resources =
0843             pseries_pci_fixup_resources;
0844         ppc_md.pcibios_fixup_sriov =
0845             pseries_pci_fixup_iov_resources;
0846         ppc_md.pcibios_iov_resource_alignment =
0847             pseries_pci_iov_resource_alignment;
0848 #endif
0849     } else {
0850         /* No special idle routine */
0851         ppc_md.enable_pmcs = power4_enable_pmcs;
0852     }
0853 
0854     ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare;
0855     pseries_rng_init();
0856 }
0857 
0858 static void pseries_panic(char *str)
0859 {
0860     panic_flush_kmsg_end();
0861     rtas_os_term(str);
0862 }
0863 
0864 static int __init pSeries_init_panel(void)
0865 {
0866     /* Manually leave the kernel version on the panel. */
0867 #ifdef __BIG_ENDIAN__
0868     ppc_md.progress("Linux ppc64\n", 0);
0869 #else
0870     ppc_md.progress("Linux ppc64le\n", 0);
0871 #endif
0872     ppc_md.progress(init_utsname()->version, 0);
0873 
0874     return 0;
0875 }
0876 machine_arch_initcall(pseries, pSeries_init_panel);
0877 
0878 static int pseries_set_dabr(unsigned long dabr, unsigned long dabrx)
0879 {
0880     return plpar_hcall_norets(H_SET_DABR, dabr);
0881 }
0882 
0883 static int pseries_set_xdabr(unsigned long dabr, unsigned long dabrx)
0884 {
0885     /* Have to set at least one bit in the DABRX according to PAPR */
0886     if (dabrx == 0 && dabr == 0)
0887         dabrx = DABRX_USER;
0888     /* PAPR says we can only set kernel and user bits */
0889     dabrx &= DABRX_KERNEL | DABRX_USER;
0890 
0891     return plpar_hcall_norets(H_SET_XDABR, dabr, dabrx);
0892 }
0893 
0894 static int pseries_set_dawr(int nr, unsigned long dawr, unsigned long dawrx)
0895 {
0896     /* PAPR says we can't set HYP */
0897     dawrx &= ~DAWRX_HYP;
0898 
0899     if (nr == 0)
0900         return plpar_set_watchpoint0(dawr, dawrx);
0901     else
0902         return plpar_set_watchpoint1(dawr, dawrx);
0903 }
0904 
0905 #define CMO_CHARACTERISTICS_TOKEN 44
0906 #define CMO_MAXLENGTH 1026
0907 
0908 void pSeries_coalesce_init(void)
0909 {
0910     struct hvcall_mpp_x_data mpp_x_data;
0911 
0912     if (firmware_has_feature(FW_FEATURE_CMO) && !h_get_mpp_x(&mpp_x_data))
0913         powerpc_firmware_features |= FW_FEATURE_XCMO;
0914     else
0915         powerpc_firmware_features &= ~FW_FEATURE_XCMO;
0916 }
0917 
0918 /**
0919  * fw_cmo_feature_init - FW_FEATURE_CMO is not stored in ibm,hypertas-functions,
0920  * handle that here. (Stolen from parse_system_parameter_string)
0921  */
0922 static void __init pSeries_cmo_feature_init(void)
0923 {
0924     char *ptr, *key, *value, *end;
0925     int call_status;
0926     int page_order = IOMMU_PAGE_SHIFT_4K;
0927 
0928     pr_debug(" -> fw_cmo_feature_init()\n");
0929     spin_lock(&rtas_data_buf_lock);
0930     memset(rtas_data_buf, 0, RTAS_DATA_BUF_SIZE);
0931     call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1,
0932                 NULL,
0933                 CMO_CHARACTERISTICS_TOKEN,
0934                 __pa(rtas_data_buf),
0935                 RTAS_DATA_BUF_SIZE);
0936 
0937     if (call_status != 0) {
0938         spin_unlock(&rtas_data_buf_lock);
0939         pr_debug("CMO not available\n");
0940         pr_debug(" <- fw_cmo_feature_init()\n");
0941         return;
0942     }
0943 
0944     end = rtas_data_buf + CMO_MAXLENGTH - 2;
0945     ptr = rtas_data_buf + 2;    /* step over strlen value */
0946     key = value = ptr;
0947 
0948     while (*ptr && (ptr <= end)) {
0949         /* Separate the key and value by replacing '=' with '\0' and
0950          * point the value at the string after the '='
0951          */
0952         if (ptr[0] == '=') {
0953             ptr[0] = '\0';
0954             value = ptr + 1;
0955         } else if (ptr[0] == '\0' || ptr[0] == ',') {
0956             /* Terminate the string containing the key/value pair */
0957             ptr[0] = '\0';
0958 
0959             if (key == value) {
0960                 pr_debug("Malformed key/value pair\n");
0961                 /* Never found a '=', end processing */
0962                 break;
0963             }
0964 
0965             if (0 == strcmp(key, "CMOPageSize"))
0966                 page_order = simple_strtol(value, NULL, 10);
0967             else if (0 == strcmp(key, "PrPSP"))
0968                 CMO_PrPSP = simple_strtol(value, NULL, 10);
0969             else if (0 == strcmp(key, "SecPSP"))
0970                 CMO_SecPSP = simple_strtol(value, NULL, 10);
0971             value = key = ptr + 1;
0972         }
0973         ptr++;
0974     }
0975 
0976     /* Page size is returned as the power of 2 of the page size,
0977      * convert to the page size in bytes before returning
0978      */
0979     CMO_PageSize = 1 << page_order;
0980     pr_debug("CMO_PageSize = %lu\n", CMO_PageSize);
0981 
0982     if (CMO_PrPSP != -1 || CMO_SecPSP != -1) {
0983         pr_info("CMO enabled\n");
0984         pr_debug("CMO enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP,
0985                  CMO_SecPSP);
0986         powerpc_firmware_features |= FW_FEATURE_CMO;
0987         pSeries_coalesce_init();
0988     } else
0989         pr_debug("CMO not enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP,
0990                  CMO_SecPSP);
0991     spin_unlock(&rtas_data_buf_lock);
0992     pr_debug(" <- fw_cmo_feature_init()\n");
0993 }
0994 
0995 /*
0996  * Early initialization.  Relocation is on but do not reference unbolted pages
0997  */
0998 static void __init pseries_init(void)
0999 {
1000     pr_debug(" -> pseries_init()\n");
1001 
1002 #ifdef CONFIG_HVC_CONSOLE
1003     if (firmware_has_feature(FW_FEATURE_LPAR))
1004         hvc_vio_init_early();
1005 #endif
1006     if (firmware_has_feature(FW_FEATURE_XDABR))
1007         ppc_md.set_dabr = pseries_set_xdabr;
1008     else if (firmware_has_feature(FW_FEATURE_DABR))
1009         ppc_md.set_dabr = pseries_set_dabr;
1010 
1011     if (firmware_has_feature(FW_FEATURE_SET_MODE))
1012         ppc_md.set_dawr = pseries_set_dawr;
1013 
1014     pSeries_cmo_feature_init();
1015     iommu_init_early_pSeries();
1016 
1017     pr_debug(" <- pseries_init()\n");
1018 }
1019 
1020 /**
1021  * pseries_power_off - tell firmware about how to power off the system.
1022  *
1023  * This function calls either the power-off rtas token in normal cases
1024  * or the ibm,power-off-ups token (if present & requested) in case of
1025  * a power failure. If power-off token is used, power on will only be
1026  * possible with power button press. If ibm,power-off-ups token is used
1027  * it will allow auto poweron after power is restored.
1028  */
1029 static void pseries_power_off(void)
1030 {
1031     int rc;
1032     int rtas_poweroff_ups_token = rtas_token("ibm,power-off-ups");
1033 
1034     if (rtas_flash_term_hook)
1035         rtas_flash_term_hook(SYS_POWER_OFF);
1036 
1037     if (rtas_poweron_auto == 0 ||
1038         rtas_poweroff_ups_token == RTAS_UNKNOWN_SERVICE) {
1039         rc = rtas_call(rtas_token("power-off"), 2, 1, NULL, -1, -1);
1040         printk(KERN_INFO "RTAS power-off returned %d\n", rc);
1041     } else {
1042         rc = rtas_call(rtas_poweroff_ups_token, 0, 1, NULL);
1043         printk(KERN_INFO "RTAS ibm,power-off-ups returned %d\n", rc);
1044     }
1045     for (;;);
1046 }
1047 
1048 static int __init pSeries_probe(void)
1049 {
1050     if (!of_node_is_type(of_root, "chrp"))
1051         return 0;
1052 
1053     /* Cell blades firmware claims to be chrp while it's not. Until this
1054      * is fixed, we need to avoid those here.
1055      */
1056     if (of_machine_is_compatible("IBM,CPBW-1.0") ||
1057         of_machine_is_compatible("IBM,CBEA"))
1058         return 0;
1059 
1060     pm_power_off = pseries_power_off;
1061 
1062     pr_debug("Machine is%s LPAR !\n",
1063              (powerpc_firmware_features & FW_FEATURE_LPAR) ? "" : " not");
1064 
1065     pseries_init();
1066 
1067     return 1;
1068 }
1069 
1070 static int pSeries_pci_probe_mode(struct pci_bus *bus)
1071 {
1072     if (firmware_has_feature(FW_FEATURE_LPAR))
1073         return PCI_PROBE_DEVTREE;
1074     return PCI_PROBE_NORMAL;
1075 }
1076 
1077 struct pci_controller_ops pseries_pci_controller_ops = {
1078     .probe_mode     = pSeries_pci_probe_mode,
1079 };
1080 
1081 define_machine(pseries) {
1082     .name           = "pSeries",
1083     .probe          = pSeries_probe,
1084     .setup_arch     = pSeries_setup_arch,
1085     .init_IRQ       = pseries_init_irq,
1086     .show_cpuinfo       = pSeries_show_cpuinfo,
1087     .log_error      = pSeries_log_error,
1088     .discover_phbs      = pSeries_discover_phbs,
1089     .pcibios_fixup      = pSeries_final_fixup,
1090     .restart        = rtas_restart,
1091     .halt           = rtas_halt,
1092     .panic          = pseries_panic,
1093     .get_boot_time      = rtas_get_boot_time,
1094     .get_rtc_time       = rtas_get_rtc_time,
1095     .set_rtc_time       = rtas_set_rtc_time,
1096     .calibrate_decr     = generic_calibrate_decr,
1097     .progress       = rtas_progress,
1098     .system_reset_exception = pSeries_system_reset_exception,
1099     .machine_check_early    = pseries_machine_check_realmode,
1100     .machine_check_exception = pSeries_machine_check_exception,
1101     .machine_check_log_err  = pSeries_machine_check_log_err,
1102 #ifdef CONFIG_KEXEC_CORE
1103     .machine_kexec          = pseries_machine_kexec,
1104     .kexec_cpu_down         = pseries_kexec_cpu_down,
1105 #endif
1106 #ifdef CONFIG_MEMORY_HOTPLUG
1107     .memory_block_size  = pseries_memory_block_size,
1108 #endif
1109 };
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