platforms/pseries/pci.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
0004  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
0005  *
0006  * pSeries specific routines for PCI.
0007  */
0008
0009 #include <linux/init.h>
0010 #include <linux/ioport.h>
0011 #include <linux/kernel.h>
0012 #include <linux/pci.h>
0013 #include <linux/string.h>
0014
0015 #include <asm/eeh.h>
0016 #include <asm/pci-bridge.h>
0017 #include <asm/ppc-pci.h>
0018 #include <asm/pci.h>
0019 #include "pseries.h"
0020
0021 #if 0
0022 void pcibios_name_device(struct pci_dev *dev)
0023 {
0024     struct device_node *dn;
0025
0026     /*
0027      * Add IBM loc code (slot) as a prefix to the device names for service
0028      */
0029     dn = pci_device_to_OF_node(dev);
0030     if (dn) {
0031         const char *loc_code = of_get_property(dn, "ibm,loc-code",
0032                 NULL);
0033         if (loc_code) {
0034             int loc_len = strlen(loc_code);
0035             if (loc_len < sizeof(dev->dev.name)) {
0036                 memmove(dev->dev.name+loc_len+1, dev->dev.name,
0037                     sizeof(dev->dev.name)-loc_len-1);
0038                 memcpy(dev->dev.name, loc_code, loc_len);
0039                 dev->dev.name[loc_len] = ' ';
0040                 dev->dev.name[sizeof(dev->dev.name)-1] = '\0';
0041             }
0042         }
0043     }
0044 }
0045 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device);
0046 #endif
0047
0048 #ifdef CONFIG_PCI_IOV
0049 #define MAX_VFS_FOR_MAP_PE 256
0050 struct pe_map_bar_entry {
0051     __be64     bar;       /* Input:  Virtual Function BAR */
0052     __be16     rid;       /* Input:  Virtual Function Router ID */
0053     __be16     pe_num;    /* Output: Virtual Function PE Number */
0054     __be32     reserved;  /* Reserved Space */
0055 };
0056
0057 static int pseries_send_map_pe(struct pci_dev *pdev, u16 num_vfs,
0058                    struct pe_map_bar_entry *vf_pe_array)
0059 {
0060     struct pci_dn *pdn;
0061     int rc;
0062     unsigned long buid, addr;
0063     int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number");
0064
0065     if (ibm_map_pes == RTAS_UNKNOWN_SERVICE)
0066         return -EINVAL;
0067
0068     pdn = pci_get_pdn(pdev);
0069     addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
0070     buid = pdn->phb->buid;
0071     spin_lock(&rtas_data_buf_lock);
0072     memcpy(rtas_data_buf, vf_pe_array,
0073            RTAS_DATA_BUF_SIZE);
0074     rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr,
0075                BUID_HI(buid), BUID_LO(buid),
0076                rtas_data_buf,
0077                num_vfs * sizeof(struct pe_map_bar_entry));
0078     memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE);
0079     spin_unlock(&rtas_data_buf_lock);
0080
0081     if (rc)
0082         dev_err(&pdev->dev,
0083             "%s: Failed to associate pes PE#%lx, rc=%x\n",
0084             __func__,  addr, rc);
0085
0086     return rc;
0087 }
0088
0089 static void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num)
0090 {
0091     struct pci_dn *pdn;
0092
0093     pdn = pci_get_pdn(pdev);
0094     pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num);
0095     dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n",
0096         pci_domain_nr(pdev->bus),
0097         pdev->bus->number,
0098         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
0099         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)),
0100         pdn->pe_num_map[vf_index]);
0101 }
0102
0103 static int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs)
0104 {
0105     struct pci_dn *pdn;
0106     int i, rc, vf_index;
0107     struct pe_map_bar_entry *vf_pe_array;
0108     struct resource *res;
0109     u64 size;
0110
0111     vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
0112     if (!vf_pe_array)
0113         return -ENOMEM;
0114
0115     pdn = pci_get_pdn(pdev);
0116     /* create firmware structure to associate pes */
0117     for (vf_index = 0; vf_index < num_vfs; vf_index++) {
0118         pdn->pe_num_map[vf_index] = IODA_INVALID_PE;
0119         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
0120             res = &pdev->resource[i + PCI_IOV_RESOURCES];
0121             if (!res->parent)
0122                 continue;
0123             size = pcibios_iov_resource_alignment(pdev, i +
0124                     PCI_IOV_RESOURCES);
0125             vf_pe_array[vf_index].bar =
0126                 cpu_to_be64(res->start + size * vf_index);
0127             vf_pe_array[vf_index].rid =
0128                 cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index)
0129                         << 8) | pci_iov_virtfn_devfn(pdev,
0130                         vf_index));
0131             vf_pe_array[vf_index].pe_num =
0132                 cpu_to_be16(IODA_INVALID_PE);
0133         }
0134     }
0135
0136     rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array);
0137     /* Only zero is success */
0138     if (!rc)
0139         for (vf_index = 0; vf_index < num_vfs; vf_index++)
0140             pseries_set_pe_num(pdev, vf_index,
0141                        vf_pe_array[vf_index].pe_num);
0142
0143     kfree(vf_pe_array);
0144     return rc;
0145 }
0146
0147 static int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
0148 {
0149     struct pci_dn         *pdn;
0150     int                    rc;
0151     const int *max_vfs;
0152     int max_config_vfs;
0153     struct device_node *dn = pci_device_to_OF_node(pdev);
0154
0155     max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL);
0156
0157     if (!max_vfs)
0158         return -EINVAL;
0159
0160     /* First integer stores max config */
0161     max_config_vfs = of_read_number(&max_vfs[0], 1);
0162     if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) {
0163         dev_err(&pdev->dev,
0164             "Num VFs %x > %x Configurable VFs\n",
0165             num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ?
0166             MAX_VFS_FOR_MAP_PE : max_config_vfs);
0167         return -EINVAL;
0168     }
0169
0170     pdn = pci_get_pdn(pdev);
0171     pdn->pe_num_map = kmalloc_array(num_vfs,
0172                     sizeof(*pdn->pe_num_map),
0173                     GFP_KERNEL);
0174     if (!pdn->pe_num_map)
0175         return -ENOMEM;
0176
0177     rc = pseries_associate_pes(pdev, num_vfs);
0178
0179     /* Anything other than zero is failure */
0180     if (rc) {
0181         dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc);
0182         kfree(pdn->pe_num_map);
0183     } else {
0184         pci_vf_drivers_autoprobe(pdev, false);
0185     }
0186
0187     return rc;
0188 }
0189
0190 static int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
0191 {
0192     /* Allocate PCI data */
0193     add_sriov_vf_pdns(pdev);
0194     return pseries_pci_sriov_enable(pdev, num_vfs);
0195 }
0196
0197 static int pseries_pcibios_sriov_disable(struct pci_dev *pdev)
0198 {
0199     struct pci_dn         *pdn;
0200
0201     pdn = pci_get_pdn(pdev);
0202     /* Releasing pe_num_map */
0203     kfree(pdn->pe_num_map);
0204     /* Release PCI data */
0205     remove_sriov_vf_pdns(pdev);
0206     pci_vf_drivers_autoprobe(pdev, true);
0207     return 0;
0208 }
0209 #endif
0210
0211 static void __init pSeries_request_regions(void)
0212 {
0213     if (!isa_io_base)
0214         return;
0215
0216     request_region(0x20,0x20,"pic1");
0217     request_region(0xa0,0x20,"pic2");
0218     request_region(0x00,0x20,"dma1");
0219     request_region(0x40,0x20,"timer");
0220     request_region(0x80,0x10,"dma page reg");
0221     request_region(0xc0,0x20,"dma2");
0222 }
0223
0224 void __init pSeries_final_fixup(void)
0225 {
0226     pSeries_request_regions();
0227
0228     eeh_show_enabled();
0229
0230 #ifdef CONFIG_PCI_IOV
0231     ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable;
0232     ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable;
0233 #endif
0234 }
0235
0236 /*
0237  * Assume the winbond 82c105 is the IDE controller on a
0238  * p610/p615/p630. We should probably be more careful in case
0239  * someone tries to plug in a similar adapter.
0240  */
0241 static void fixup_winbond_82c105(struct pci_dev* dev)
0242 {
0243     int i;
0244     unsigned int reg;
0245
0246     if (!machine_is(pseries))
0247         return;
0248
0249     printk("Using INTC for W82c105 IDE controller.\n");
0250     pci_read_config_dword(dev, 0x40, &reg);
0251     /* Enable LEGIRQ to use INTC instead of ISA interrupts */
0252     pci_write_config_dword(dev, 0x40, reg | (1<<11));
0253
0254     for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
0255         /* zap the 2nd function of the winbond chip */
0256         if (dev->resource[i].flags & IORESOURCE_IO
0257             && dev->bus->number == 0 && dev->devfn == 0x81)
0258             dev->resource[i].flags &= ~IORESOURCE_IO;
0259         if (dev->resource[i].start == 0 && dev->resource[i].end) {
0260             dev->resource[i].flags = 0;
0261             dev->resource[i].end = 0;
0262         }
0263     }
0264 }
0265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
0266              fixup_winbond_82c105);
0267
0268 static enum pci_bus_speed prop_to_pci_speed(u32 prop)
0269 {
0270     switch (prop) {
0271     case 0x01:
0272         return PCIE_SPEED_2_5GT;
0273     case 0x02:
0274         return PCIE_SPEED_5_0GT;
0275     case 0x04:
0276         return PCIE_SPEED_8_0GT;
0277     case 0x08:
0278         return PCIE_SPEED_16_0GT;
0279     case 0x10:
0280         return PCIE_SPEED_32_0GT;
0281     default:
0282         pr_debug("Unexpected PCI link speed property value\n");
0283         return PCI_SPEED_UNKNOWN;
0284     }
0285 }
0286
0287 int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
0288 {
0289     struct device_node *dn, *pdn;
0290     struct pci_bus *bus;
0291     u32 pcie_link_speed_stats[2];
0292     int rc;
0293
0294     bus = bridge->bus;
0295
0296     /* Rely on the pcibios_free_controller_deferred() callback. */
0297     pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred,
0298                     (void *) pci_bus_to_host(bus));
0299
0300     dn = pcibios_get_phb_of_node(bus);
0301     if (!dn)
0302         return 0;
0303
0304     for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
0305         rc = of_property_read_u32_array(pdn,
0306                 "ibm,pcie-link-speed-stats",
0307                 &pcie_link_speed_stats[0], 2);
0308         if (!rc)
0309             break;
0310     }
0311
0312     of_node_put(pdn);
0313
0314     if (rc) {
0315         pr_debug("no ibm,pcie-link-speed-stats property\n");
0316         return 0;
0317     }
0318
0319     bus->max_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[0]);
0320     bus->cur_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[1]);
0321     return 0;
0322 }