platforms/pseries/eeh_pseries.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * The file intends to implement the platform dependent EEH operations on pseries.
0004  * Actually, the pseries platform is built based on RTAS heavily. That means the
0005  * pseries platform dependent EEH operations will be built on RTAS calls. The functions
0006  * are derived from arch/powerpc/platforms/pseries/eeh.c and necessary cleanup has
0007  * been done.
0008  *
0009  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2011.
0010  * Copyright IBM Corporation 2001, 2005, 2006
0011  * Copyright Dave Engebretsen & Todd Inglett 2001
0012  * Copyright Linas Vepstas 2005, 2006
0013  */
0014
0015 #include <linux/atomic.h>
0016 #include <linux/delay.h>
0017 #include <linux/export.h>
0018 #include <linux/init.h>
0019 #include <linux/list.h>
0020 #include <linux/of.h>
0021 #include <linux/pci.h>
0022 #include <linux/proc_fs.h>
0023 #include <linux/rbtree.h>
0024 #include <linux/sched.h>
0025 #include <linux/seq_file.h>
0026 #include <linux/spinlock.h>
0027 #include <linux/crash_dump.h>
0028
0029 #include <asm/eeh.h>
0030 #include <asm/eeh_event.h>
0031 #include <asm/io.h>
0032 #include <asm/machdep.h>
0033 #include <asm/ppc-pci.h>
0034 #include <asm/rtas.h>
0035
0036 /* RTAS tokens */
0037 static int ibm_set_eeh_option;
0038 static int ibm_set_slot_reset;
0039 static int ibm_read_slot_reset_state;
0040 static int ibm_read_slot_reset_state2;
0041 static int ibm_slot_error_detail;
0042 static int ibm_get_config_addr_info;
0043 static int ibm_get_config_addr_info2;
0044 static int ibm_configure_pe;
0045
0046 static void pseries_eeh_init_edev(struct pci_dn *pdn);
0047
0048 static void pseries_pcibios_bus_add_device(struct pci_dev *pdev)
0049 {
0050     struct pci_dn *pdn = pci_get_pdn(pdev);
0051
0052     if (eeh_has_flag(EEH_FORCE_DISABLED))
0053         return;
0054
0055     dev_dbg(&pdev->dev, "EEH: Setting up device\n");
0056 #ifdef CONFIG_PCI_IOV
0057     if (pdev->is_virtfn) {
0058         pdn->device_id  =  pdev->device;
0059         pdn->vendor_id  =  pdev->vendor;
0060         pdn->class_code =  pdev->class;
0061         /*
0062          * Last allow unfreeze return code used for retrieval
0063          * by user space in eeh-sysfs to show the last command
0064          * completion from platform.
0065          */
0066         pdn->last_allow_rc =  0;
0067     }
0068 #endif
0069     pseries_eeh_init_edev(pdn);
0070 #ifdef CONFIG_PCI_IOV
0071     if (pdev->is_virtfn) {
0072         /*
0073          * FIXME: This really should be handled by choosing the right
0074          *        parent PE in pseries_eeh_init_edev().
0075          */
0076         struct eeh_pe *physfn_pe = pci_dev_to_eeh_dev(pdev->physfn)->pe;
0077         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
0078
0079         edev->pe_config_addr =  (pdn->busno << 16) | (pdn->devfn << 8);
0080         eeh_pe_tree_remove(edev); /* Remove as it is adding to bus pe */
0081         eeh_pe_tree_insert(edev, physfn_pe);   /* Add as VF PE type */
0082     }
0083 #endif
0084     eeh_probe_device(pdev);
0085 }
0086
0087
0088 /**
0089  * pseries_eeh_get_pe_config_addr - Find the pe_config_addr for a device
0090  * @pdn: pci_dn of the input device
0091  *
0092  * The EEH RTAS calls use a tuple consisting of: (buid_hi, buid_lo,
0093  * pe_config_addr) as a handle to a given PE. This function finds the
0094  * pe_config_addr based on the device's config addr.
0095  *
0096  * Keep in mind that the pe_config_addr *might* be numerically identical to the
0097  * device's config addr, but the two are conceptually distinct.
0098  *
0099  * Returns the pe_config_addr, or a negative error code.
0100  */
0101 static int pseries_eeh_get_pe_config_addr(struct pci_dn *pdn)
0102 {
0103     int config_addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
0104     struct pci_controller *phb = pdn->phb;
0105     int ret, rets[3];
0106
0107     if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
0108         /*
0109          * First of all, use function 1 to determine if this device is
0110          * part of a PE or not. ret[0] being zero indicates it's not.
0111          */
0112         ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
0113                 config_addr, BUID_HI(phb->buid),
0114                 BUID_LO(phb->buid), 1);
0115         if (ret || (rets[0] == 0))
0116             return -ENOENT;
0117
0118         /* Retrieve the associated PE config address with function 0 */
0119         ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
0120                 config_addr, BUID_HI(phb->buid),
0121                 BUID_LO(phb->buid), 0);
0122         if (ret) {
0123             pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
0124                 __func__, phb->global_number, config_addr);
0125             return -ENXIO;
0126         }
0127
0128         return rets[0];
0129     }
0130
0131     if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
0132         ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
0133                 config_addr, BUID_HI(phb->buid),
0134                 BUID_LO(phb->buid), 0);
0135         if (ret) {
0136             pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
0137                 __func__, phb->global_number, config_addr);
0138             return -ENXIO;
0139         }
0140
0141         return rets[0];
0142     }
0143
0144     /*
0145      * PAPR does describe a process for finding the pe_config_addr that was
0146      * used before the ibm,get-config-addr-info calls were added. However,
0147      * I haven't found *any* systems that don't have that RTAS call
0148      * implemented. If you happen to find one that needs the old DT based
0149      * process, patches are welcome!
0150      */
0151     return -ENOENT;
0152 }
0153
0154 /**
0155  * pseries_eeh_phb_reset - Reset the specified PHB
0156  * @phb: PCI controller
0157  * @config_adddr: the associated config address
0158  * @option: reset option
0159  *
0160  * Reset the specified PHB/PE
0161  */
0162 static int pseries_eeh_phb_reset(struct pci_controller *phb, int config_addr, int option)
0163 {
0164     int ret;
0165
0166     /* Reset PE through RTAS call */
0167     ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
0168             config_addr, BUID_HI(phb->buid),
0169             BUID_LO(phb->buid), option);
0170
0171     /* If fundamental-reset not supported, try hot-reset */
0172     if (option == EEH_RESET_FUNDAMENTAL && ret == -8) {
0173         option = EEH_RESET_HOT;
0174         ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
0175                 config_addr, BUID_HI(phb->buid),
0176                 BUID_LO(phb->buid), option);
0177     }
0178
0179     /* We need reset hold or settlement delay */
0180     if (option == EEH_RESET_FUNDAMENTAL || option == EEH_RESET_HOT)
0181         msleep(EEH_PE_RST_HOLD_TIME);
0182     else
0183         msleep(EEH_PE_RST_SETTLE_TIME);
0184
0185     return ret;
0186 }
0187
0188 /**
0189  * pseries_eeh_phb_configure_bridge - Configure PCI bridges in the indicated PE
0190  * @phb: PCI controller
0191  * @config_adddr: the associated config address
0192  *
0193  * The function will be called to reconfigure the bridges included
0194  * in the specified PE so that the mulfunctional PE would be recovered
0195  * again.
0196  */
0197 static int pseries_eeh_phb_configure_bridge(struct pci_controller *phb, int config_addr)
0198 {
0199     int ret;
0200     /* Waiting 0.2s maximum before skipping configuration */
0201     int max_wait = 200;
0202
0203     while (max_wait > 0) {
0204         ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
0205                 config_addr, BUID_HI(phb->buid),
0206                 BUID_LO(phb->buid));
0207
0208         if (!ret)
0209             return ret;
0210         if (ret < 0)
0211             break;
0212
0213         /*
0214          * If RTAS returns a delay value that's above 100ms, cut it
0215          * down to 100ms in case firmware made a mistake.  For more
0216          * on how these delay values work see rtas_busy_delay_time
0217          */
0218         if (ret > RTAS_EXTENDED_DELAY_MIN+2 &&
0219             ret <= RTAS_EXTENDED_DELAY_MAX)
0220             ret = RTAS_EXTENDED_DELAY_MIN+2;
0221
0222         max_wait -= rtas_busy_delay_time(ret);
0223
0224         if (max_wait < 0)
0225             break;
0226
0227         rtas_busy_delay(ret);
0228     }
0229
0230     pr_warn("%s: Unable to configure bridge PHB#%x-PE#%x (%d)\n",
0231         __func__, phb->global_number, config_addr, ret);
0232     /* PAPR defines -3 as "Parameter Error" for this function: */
0233     if (ret == -3)
0234         return -EINVAL;
0235     else
0236         return -EIO;
0237 }
0238
0239 /*
0240  * Buffer for reporting slot-error-detail rtas calls. Its here
0241  * in BSS, and not dynamically alloced, so that it ends up in
0242  * RMO where RTAS can access it.
0243  */
0244 static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
0245 static DEFINE_SPINLOCK(slot_errbuf_lock);
0246 static int eeh_error_buf_size;
0247
0248 static int pseries_eeh_cap_start(struct pci_dn *pdn)
0249 {
0250     u32 status;
0251
0252     if (!pdn)
0253         return 0;
0254
0255     rtas_read_config(pdn, PCI_STATUS, 2, &status);
0256     if (!(status & PCI_STATUS_CAP_LIST))
0257         return 0;
0258
0259     return PCI_CAPABILITY_LIST;
0260 }
0261
0262
0263 static int pseries_eeh_find_cap(struct pci_dn *pdn, int cap)
0264 {
0265     int pos = pseries_eeh_cap_start(pdn);
0266     int cnt = 48;   /* Maximal number of capabilities */
0267     u32 id;
0268
0269     if (!pos)
0270         return 0;
0271
0272         while (cnt--) {
0273         rtas_read_config(pdn, pos, 1, &pos);
0274         if (pos < 0x40)
0275             break;
0276         pos &= ~3;
0277         rtas_read_config(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
0278         if (id == 0xff)
0279             break;
0280         if (id == cap)
0281             return pos;
0282         pos += PCI_CAP_LIST_NEXT;
0283     }
0284
0285     return 0;
0286 }
0287
0288 static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
0289 {
0290     struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
0291     u32 header;
0292     int pos = 256;
0293     int ttl = (4096 - 256) / 8;
0294
0295     if (!edev || !edev->pcie_cap)
0296         return 0;
0297     if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
0298         return 0;
0299     else if (!header)
0300         return 0;
0301
0302     while (ttl-- > 0) {
0303         if (PCI_EXT_CAP_ID(header) == cap && pos)
0304             return pos;
0305
0306         pos = PCI_EXT_CAP_NEXT(header);
0307         if (pos < 256)
0308             break;
0309
0310         if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
0311             break;
0312     }
0313
0314     return 0;
0315 }
0316
0317 /**
0318  * pseries_eeh_pe_get_parent - Retrieve the parent PE
0319  * @edev: EEH device
0320  *
0321  * The whole PEs existing in the system are organized as hierarchy
0322  * tree. The function is used to retrieve the parent PE according
0323  * to the parent EEH device.
0324  */
0325 static struct eeh_pe *pseries_eeh_pe_get_parent(struct eeh_dev *edev)
0326 {
0327     struct eeh_dev *parent;
0328     struct pci_dn *pdn = eeh_dev_to_pdn(edev);
0329
0330     /*
0331      * It might have the case for the indirect parent
0332      * EEH device already having associated PE, but
0333      * the direct parent EEH device doesn't have yet.
0334      */
0335     if (edev->physfn)
0336         pdn = pci_get_pdn(edev->physfn);
0337     else
0338         pdn = pdn ? pdn->parent : NULL;
0339     while (pdn) {
0340         /* We're poking out of PCI territory */
0341         parent = pdn_to_eeh_dev(pdn);
0342         if (!parent)
0343             return NULL;
0344
0345         if (parent->pe)
0346             return parent->pe;
0347
0348         pdn = pdn->parent;
0349     }
0350
0351     return NULL;
0352 }
0353
0354 /**
0355  * pseries_eeh_init_edev - initialise the eeh_dev and eeh_pe for a pci_dn
0356  *
0357  * @pdn: PCI device node
0358  *
0359  * When we discover a new PCI device via the device-tree we create a
0360  * corresponding pci_dn and we allocate, but don't initialise, an eeh_dev.
0361  * This function takes care of the initialisation and inserts the eeh_dev
0362  * into the correct eeh_pe. If no eeh_pe exists we'll allocate one.
0363  */
0364 static void pseries_eeh_init_edev(struct pci_dn *pdn)
0365 {
0366     struct eeh_pe pe, *parent;
0367     struct eeh_dev *edev;
0368     u32 pcie_flags;
0369     int ret;
0370
0371     if (WARN_ON_ONCE(!eeh_has_flag(EEH_PROBE_MODE_DEVTREE)))
0372         return;
0373
0374     /*
0375      * Find the eeh_dev for this pdn. The storage for the eeh_dev was
0376      * allocated at the same time as the pci_dn.
0377      *
0378      * XXX: We should probably re-visit that.
0379      */
0380     edev = pdn_to_eeh_dev(pdn);
0381     if (!edev)
0382         return;
0383
0384     /*
0385      * If ->pe is set then we've already probed this device. We hit
0386      * this path when a pci_dev is removed and rescanned while recovering
0387      * a PE (i.e. for devices where the driver doesn't support error
0388      * recovery).
0389      */
0390     if (edev->pe)
0391         return;
0392
0393     /* Check class/vendor/device IDs */
0394     if (!pdn->vendor_id || !pdn->device_id || !pdn->class_code)
0395         return;
0396
0397     /* Skip for PCI-ISA bridge */
0398         if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
0399         return;
0400
0401     eeh_edev_dbg(edev, "Probing device\n");
0402
0403     /*
0404      * Update class code and mode of eeh device. We need
0405      * correctly reflects that current device is root port
0406      * or PCIe switch downstream port.
0407      */
0408     edev->pcix_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
0409     edev->pcie_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
0410     edev->aer_cap = pseries_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
0411     edev->mode &= 0xFFFFFF00;
0412     if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
0413         edev->mode |= EEH_DEV_BRIDGE;
0414         if (edev->pcie_cap) {
0415             rtas_read_config(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
0416                      2, &pcie_flags);
0417             pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
0418             if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
0419                 edev->mode |= EEH_DEV_ROOT_PORT;
0420             else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
0421                 edev->mode |= EEH_DEV_DS_PORT;
0422         }
0423     }
0424
0425     /* first up, find the pe_config_addr for the PE containing the device */
0426     ret = pseries_eeh_get_pe_config_addr(pdn);
0427     if (ret < 0) {
0428         eeh_edev_dbg(edev, "Unable to find pe_config_addr\n");
0429         goto err;
0430     }
0431
0432     /* Try enable EEH on the fake PE */
0433     memset(&pe, 0, sizeof(struct eeh_pe));
0434     pe.phb = pdn->phb;
0435     pe.addr = ret;
0436
0437     eeh_edev_dbg(edev, "Enabling EEH on device\n");
0438     ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
0439     if (ret) {
0440         eeh_edev_dbg(edev, "EEH failed to enable on device (code %d)\n", ret);
0441         goto err;
0442     }
0443
0444     edev->pe_config_addr = pe.addr;
0445
0446     eeh_add_flag(EEH_ENABLED);
0447
0448     parent = pseries_eeh_pe_get_parent(edev);
0449     eeh_pe_tree_insert(edev, parent);
0450     eeh_save_bars(edev);
0451     eeh_edev_dbg(edev, "EEH enabled for device");
0452
0453     return;
0454
0455 err:
0456     eeh_edev_dbg(edev, "EEH is unsupported on device (code = %d)\n", ret);
0457 }
0458
0459 static struct eeh_dev *pseries_eeh_probe(struct pci_dev *pdev)
0460 {
0461     struct eeh_dev *edev;
0462     struct pci_dn *pdn;
0463
0464     pdn = pci_get_pdn_by_devfn(pdev->bus, pdev->devfn);
0465     if (!pdn)
0466         return NULL;
0467
0468     /*
0469      * If the system supports EEH on this device then the eeh_dev was
0470      * configured and inserted into a PE in pseries_eeh_init_edev()
0471      */
0472     edev = pdn_to_eeh_dev(pdn);
0473     if (!edev || !edev->pe)
0474         return NULL;
0475
0476     return edev;
0477 }
0478
0479 /**
0480  * pseries_eeh_init_edev_recursive - Enable EEH for the indicated device
0481  * @pdn: PCI device node
0482  *
0483  * This routine must be used to perform EEH initialization for the
0484  * indicated PCI device that was added after system boot (e.g.
0485  * hotplug, dlpar).
0486  */
0487 void pseries_eeh_init_edev_recursive(struct pci_dn *pdn)
0488 {
0489     struct pci_dn *n;
0490
0491     if (!pdn)
0492         return;
0493
0494     list_for_each_entry(n, &pdn->child_list, list)
0495         pseries_eeh_init_edev_recursive(n);
0496
0497     pseries_eeh_init_edev(pdn);
0498 }
0499 EXPORT_SYMBOL_GPL(pseries_eeh_init_edev_recursive);
0500
0501 /**
0502  * pseries_eeh_set_option - Initialize EEH or MMIO/DMA reenable
0503  * @pe: EEH PE
0504  * @option: operation to be issued
0505  *
0506  * The function is used to control the EEH functionality globally.
0507  * Currently, following options are support according to PAPR:
0508  * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
0509  */
0510 static int pseries_eeh_set_option(struct eeh_pe *pe, int option)
0511 {
0512     int ret = 0;
0513
0514     /*
0515      * When we're enabling or disabling EEH functionality on
0516      * the particular PE, the PE config address is possibly
0517      * unavailable. Therefore, we have to figure it out from
0518      * the FDT node.
0519      */
0520     switch (option) {
0521     case EEH_OPT_DISABLE:
0522     case EEH_OPT_ENABLE:
0523     case EEH_OPT_THAW_MMIO:
0524     case EEH_OPT_THAW_DMA:
0525         break;
0526     case EEH_OPT_FREEZE_PE:
0527         /* Not support */
0528         return 0;
0529     default:
0530         pr_err("%s: Invalid option %d\n", __func__, option);
0531         return -EINVAL;
0532     }
0533
0534     ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
0535             pe->addr, BUID_HI(pe->phb->buid),
0536             BUID_LO(pe->phb->buid), option);
0537
0538     return ret;
0539 }
0540
0541 /**
0542  * pseries_eeh_get_state - Retrieve PE state
0543  * @pe: EEH PE
0544  * @delay: suggested time to wait if state is unavailable
0545  *
0546  * Retrieve the state of the specified PE. On RTAS compliant
0547  * pseries platform, there already has one dedicated RTAS function
0548  * for the purpose. It's notable that the associated PE config address
0549  * might be ready when calling the function. Therefore, endeavour to
0550  * use the PE config address if possible. Further more, there're 2
0551  * RTAS calls for the purpose, we need to try the new one and back
0552  * to the old one if the new one couldn't work properly.
0553  */
0554 static int pseries_eeh_get_state(struct eeh_pe *pe, int *delay)
0555 {
0556     int ret;
0557     int rets[4];
0558     int result;
0559
0560     if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
0561         ret = rtas_call(ibm_read_slot_reset_state2, 3, 4, rets,
0562                 pe->addr, BUID_HI(pe->phb->buid),
0563                 BUID_LO(pe->phb->buid));
0564     } else if (ibm_read_slot_reset_state != RTAS_UNKNOWN_SERVICE) {
0565         /* Fake PE unavailable info */
0566         rets[2] = 0;
0567         ret = rtas_call(ibm_read_slot_reset_state, 3, 3, rets,
0568                 pe->addr, BUID_HI(pe->phb->buid),
0569                 BUID_LO(pe->phb->buid));
0570     } else {
0571         return EEH_STATE_NOT_SUPPORT;
0572     }
0573
0574     if (ret)
0575         return ret;
0576
0577     /* Parse the result out */
0578     if (!rets[1])
0579         return EEH_STATE_NOT_SUPPORT;
0580
0581     switch(rets[0]) {
0582     case 0:
0583         result = EEH_STATE_MMIO_ACTIVE |
0584              EEH_STATE_DMA_ACTIVE;
0585         break;
0586     case 1:
0587         result = EEH_STATE_RESET_ACTIVE |
0588              EEH_STATE_MMIO_ACTIVE  |
0589              EEH_STATE_DMA_ACTIVE;
0590         break;
0591     case 2:
0592         result = 0;
0593         break;
0594     case 4:
0595         result = EEH_STATE_MMIO_ENABLED;
0596         break;
0597     case 5:
0598         if (rets[2]) {
0599             if (delay)
0600                 *delay = rets[2];
0601             result = EEH_STATE_UNAVAILABLE;
0602         } else {
0603             result = EEH_STATE_NOT_SUPPORT;
0604         }
0605         break;
0606     default:
0607         result = EEH_STATE_NOT_SUPPORT;
0608     }
0609
0610     return result;
0611 }
0612
0613 /**
0614  * pseries_eeh_reset - Reset the specified PE
0615  * @pe: EEH PE
0616  * @option: reset option
0617  *
0618  * Reset the specified PE
0619  */
0620 static int pseries_eeh_reset(struct eeh_pe *pe, int option)
0621 {
0622     return pseries_eeh_phb_reset(pe->phb, pe->addr, option);
0623 }
0624
0625 /**
0626  * pseries_eeh_get_log - Retrieve error log
0627  * @pe: EEH PE
0628  * @severity: temporary or permanent error log
0629  * @drv_log: driver log to be combined with retrieved error log
0630  * @len: length of driver log
0631  *
0632  * Retrieve the temporary or permanent error from the PE.
0633  * Actually, the error will be retrieved through the dedicated
0634  * RTAS call.
0635  */
0636 static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len)
0637 {
0638     unsigned long flags;
0639     int ret;
0640
0641     spin_lock_irqsave(&slot_errbuf_lock, flags);
0642     memset(slot_errbuf, 0, eeh_error_buf_size);
0643
0644     ret = rtas_call(ibm_slot_error_detail, 8, 1, NULL, pe->addr,
0645             BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid),
0646             virt_to_phys(drv_log), len,
0647             virt_to_phys(slot_errbuf), eeh_error_buf_size,
0648             severity);
0649     if (!ret)
0650         log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
0651     spin_unlock_irqrestore(&slot_errbuf_lock, flags);
0652
0653     return ret;
0654 }
0655
0656 /**
0657  * pseries_eeh_configure_bridge - Configure PCI bridges in the indicated PE
0658  * @pe: EEH PE
0659  *
0660  */
0661 static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
0662 {
0663     return pseries_eeh_phb_configure_bridge(pe->phb, pe->addr);
0664 }
0665
0666 /**
0667  * pseries_eeh_read_config - Read PCI config space
0668  * @edev: EEH device handle
0669  * @where: PCI config space offset
0670  * @size: size to read
0671  * @val: return value
0672  *
0673  * Read config space from the speicifed device
0674  */
0675 static int pseries_eeh_read_config(struct eeh_dev *edev, int where, int size, u32 *val)
0676 {
0677     struct pci_dn *pdn = eeh_dev_to_pdn(edev);
0678
0679     return rtas_read_config(pdn, where, size, val);
0680 }
0681
0682 /**
0683  * pseries_eeh_write_config - Write PCI config space
0684  * @edev: EEH device handle
0685  * @where: PCI config space offset
0686  * @size: size to write
0687  * @val: value to be written
0688  *
0689  * Write config space to the specified device
0690  */
0691 static int pseries_eeh_write_config(struct eeh_dev *edev, int where, int size, u32 val)
0692 {
0693     struct pci_dn *pdn = eeh_dev_to_pdn(edev);
0694
0695     return rtas_write_config(pdn, where, size, val);
0696 }
0697
0698 #ifdef CONFIG_PCI_IOV
0699 static int pseries_send_allow_unfreeze(struct pci_dn *pdn, u16 *vf_pe_array, int cur_vfs)
0700 {
0701     int rc;
0702     int ibm_allow_unfreeze = rtas_token("ibm,open-sriov-allow-unfreeze");
0703     unsigned long buid, addr;
0704
0705     addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
0706     buid = pdn->phb->buid;
0707     spin_lock(&rtas_data_buf_lock);
0708     memcpy(rtas_data_buf, vf_pe_array, RTAS_DATA_BUF_SIZE);
0709     rc = rtas_call(ibm_allow_unfreeze, 5, 1, NULL,
0710                addr,
0711                BUID_HI(buid),
0712                BUID_LO(buid),
0713                rtas_data_buf, cur_vfs * sizeof(u16));
0714     spin_unlock(&rtas_data_buf_lock);
0715     if (rc)
0716         pr_warn("%s: Failed to allow unfreeze for PHB#%x-PE#%lx, rc=%x\n",
0717             __func__,
0718             pdn->phb->global_number, addr, rc);
0719     return rc;
0720 }
0721
0722 static int pseries_call_allow_unfreeze(struct eeh_dev *edev)
0723 {
0724     int cur_vfs = 0, rc = 0, vf_index, bus, devfn, vf_pe_num;
0725     struct pci_dn *pdn, *tmp, *parent, *physfn_pdn;
0726     u16 *vf_pe_array;
0727
0728     vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
0729     if (!vf_pe_array)
0730         return -ENOMEM;
0731     if (pci_num_vf(edev->physfn ? edev->physfn : edev->pdev)) {
0732         if (edev->pdev->is_physfn) {
0733             cur_vfs = pci_num_vf(edev->pdev);
0734             pdn = eeh_dev_to_pdn(edev);
0735             parent = pdn->parent;
0736             for (vf_index = 0; vf_index < cur_vfs; vf_index++)
0737                 vf_pe_array[vf_index] =
0738                     cpu_to_be16(pdn->pe_num_map[vf_index]);
0739             rc = pseries_send_allow_unfreeze(pdn, vf_pe_array,
0740                              cur_vfs);
0741             pdn->last_allow_rc = rc;
0742             for (vf_index = 0; vf_index < cur_vfs; vf_index++) {
0743                 list_for_each_entry_safe(pdn, tmp,
0744                              &parent->child_list,
0745                              list) {
0746                     bus = pci_iov_virtfn_bus(edev->pdev,
0747                                  vf_index);
0748                     devfn = pci_iov_virtfn_devfn(edev->pdev,
0749                                      vf_index);
0750                     if (pdn->busno != bus ||
0751                         pdn->devfn != devfn)
0752                         continue;
0753                     pdn->last_allow_rc = rc;
0754                 }
0755             }
0756         } else {
0757             pdn = pci_get_pdn(edev->pdev);
0758             physfn_pdn = pci_get_pdn(edev->physfn);
0759
0760             vf_pe_num = physfn_pdn->pe_num_map[edev->vf_index];
0761             vf_pe_array[0] = cpu_to_be16(vf_pe_num);
0762             rc = pseries_send_allow_unfreeze(physfn_pdn,
0763                              vf_pe_array, 1);
0764             pdn->last_allow_rc = rc;
0765         }
0766     }
0767
0768     kfree(vf_pe_array);
0769     return rc;
0770 }
0771
0772 static int pseries_notify_resume(struct eeh_dev *edev)
0773 {
0774     if (!edev)
0775         return -EEXIST;
0776
0777     if (rtas_token("ibm,open-sriov-allow-unfreeze") == RTAS_UNKNOWN_SERVICE)
0778         return -EINVAL;
0779
0780     if (edev->pdev->is_physfn || edev->pdev->is_virtfn)
0781         return pseries_call_allow_unfreeze(edev);
0782
0783     return 0;
0784 }
0785 #endif
0786
0787 static struct eeh_ops pseries_eeh_ops = {
0788     .name           = "pseries",
0789     .probe          = pseries_eeh_probe,
0790     .set_option     = pseries_eeh_set_option,
0791     .get_state      = pseries_eeh_get_state,
0792     .reset          = pseries_eeh_reset,
0793     .get_log        = pseries_eeh_get_log,
0794     .configure_bridge       = pseries_eeh_configure_bridge,
0795     .err_inject     = NULL,
0796     .read_config        = pseries_eeh_read_config,
0797     .write_config       = pseries_eeh_write_config,
0798     .next_error     = NULL,
0799     .restore_config     = NULL, /* NB: configure_bridge() does this */
0800 #ifdef CONFIG_PCI_IOV
0801     .notify_resume      = pseries_notify_resume
0802 #endif
0803 };
0804
0805 /**
0806  * eeh_pseries_init - Register platform dependent EEH operations
0807  *
0808  * EEH initialization on pseries platform. This function should be
0809  * called before any EEH related functions.
0810  */
0811 static int __init eeh_pseries_init(void)
0812 {
0813     struct pci_controller *phb;
0814     struct pci_dn *pdn;
0815     int ret, config_addr;
0816
0817     /* figure out EEH RTAS function call tokens */
0818     ibm_set_eeh_option      = rtas_token("ibm,set-eeh-option");
0819     ibm_set_slot_reset      = rtas_token("ibm,set-slot-reset");
0820     ibm_read_slot_reset_state2  = rtas_token("ibm,read-slot-reset-state2");
0821     ibm_read_slot_reset_state   = rtas_token("ibm,read-slot-reset-state");
0822     ibm_slot_error_detail       = rtas_token("ibm,slot-error-detail");
0823     ibm_get_config_addr_info2   = rtas_token("ibm,get-config-addr-info2");
0824     ibm_get_config_addr_info    = rtas_token("ibm,get-config-addr-info");
0825     ibm_configure_pe        = rtas_token("ibm,configure-pe");
0826
0827     /*
0828      * ibm,configure-pe and ibm,configure-bridge have the same semantics,
0829      * however ibm,configure-pe can be faster.  If we can't find
0830      * ibm,configure-pe then fall back to using ibm,configure-bridge.
0831      */
0832     if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE)
0833         ibm_configure_pe    = rtas_token("ibm,configure-bridge");
0834
0835     /*
0836      * Necessary sanity check. We needn't check "get-config-addr-info"
0837      * and its variant since the old firmware probably support address
0838      * of domain/bus/slot/function for EEH RTAS operations.
0839      */
0840     if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE      ||
0841         ibm_set_slot_reset == RTAS_UNKNOWN_SERVICE      ||
0842         (ibm_read_slot_reset_state2 == RTAS_UNKNOWN_SERVICE &&
0843          ibm_read_slot_reset_state == RTAS_UNKNOWN_SERVICE) ||
0844         ibm_slot_error_detail == RTAS_UNKNOWN_SERVICE   ||
0845         ibm_configure_pe == RTAS_UNKNOWN_SERVICE) {
0846         pr_info("EEH functionality not supported\n");
0847         return -EINVAL;
0848     }
0849
0850     /* Initialize error log size */
0851     eeh_error_buf_size = rtas_token("rtas-error-log-max");
0852     if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
0853         pr_info("%s: unknown EEH error log size\n",
0854             __func__);
0855         eeh_error_buf_size = 1024;
0856     } else if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
0857         pr_info("%s: EEH error log size %d exceeds the maximal %d\n",
0858             __func__, eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
0859         eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
0860     }
0861
0862     /* Set EEH probe mode */
0863     eeh_add_flag(EEH_PROBE_MODE_DEVTREE | EEH_ENABLE_IO_FOR_LOG);
0864
0865     /* Set EEH machine dependent code */
0866     ppc_md.pcibios_bus_add_device = pseries_pcibios_bus_add_device;
0867
0868     if (is_kdump_kernel() || reset_devices) {
0869         pr_info("Issue PHB reset ...\n");
0870         list_for_each_entry(phb, &hose_list, list_node) {
0871             // Skip if the slot is empty
0872             if (list_empty(&PCI_DN(phb->dn)->child_list))
0873                 continue;
0874
0875             pdn = list_first_entry(&PCI_DN(phb->dn)->child_list, struct pci_dn, list);
0876             config_addr = pseries_eeh_get_pe_config_addr(pdn);
0877
0878             /* invalid PE config addr */
0879             if (config_addr < 0)
0880                 continue;
0881
0882             pseries_eeh_phb_reset(phb, config_addr, EEH_RESET_FUNDAMENTAL);
0883             pseries_eeh_phb_reset(phb, config_addr, EEH_RESET_DEACTIVATE);
0884             pseries_eeh_phb_configure_bridge(phb, config_addr);
0885         }
0886     }
0887
0888     ret = eeh_init(&pseries_eeh_ops);
0889     if (!ret)
0890         pr_info("EEH: pSeries platform initialized\n");
0891     else
0892         pr_info("EEH: pSeries platform initialization failure (%d)\n",
0893             ret);
0894     return ret;
0895 }
0896 machine_arch_initcall(pseries, eeh_pseries_init);