platforms/powernv/subcore-asm.S

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2013, Michael (Ellerman|Neuling), IBM Corporation.
0004  */
0005
0006 #include <asm/asm-offsets.h>
0007 #include <asm/ppc_asm.h>
0008 #include <asm/reg.h>
0009
0010 #include "subcore.h"
0011
0012
0013 _GLOBAL(split_core_secondary_loop)
0014     /*
0015      * r3 = u8 *state, used throughout the routine
0016      * r4 = temp
0017      * r5 = temp
0018      * ..
0019      * r12 = MSR
0020      */
0021     mfmsr   r12
0022
0023     /* Disable interrupts so SRR0/1 don't get trashed */
0024     li  r4,0
0025     ori r4,r4,MSR_EE|MSR_SE|MSR_BE|MSR_RI
0026     andc    r4,r12,r4
0027     sync
0028     mtmsrd  r4
0029
0030     /* Switch to real mode and leave interrupts off */
0031     li  r5, MSR_IR|MSR_DR
0032     andc    r5, r4, r5
0033
0034     LOAD_REG_ADDR(r4, real_mode)
0035
0036     mtspr   SPRN_SRR0,r4
0037     mtspr   SPRN_SRR1,r5
0038     rfid
0039     b   .   /* prevent speculative execution */
0040
0041 real_mode:
0042     /* Grab values from unsplit SPRs */
0043     mfspr   r6,  SPRN_LDBAR
0044     mfspr   r7,  SPRN_PMMAR
0045     mfspr   r8,  SPRN_PMCR
0046     mfspr   r9,  SPRN_RPR
0047     mfspr   r10, SPRN_SDR1
0048
0049     /* Order reading the SPRs vs telling the primary we are ready to split */
0050     sync
0051
0052     /* Tell thread 0 we are in real mode */
0053     li  r4, SYNC_STEP_REAL_MODE
0054     stb r4, 0(r3)
0055
0056     li  r5, (HID0_POWER8_4LPARMODE | HID0_POWER8_2LPARMODE)@highest
0057     sldi    r5, r5, 48
0058
0059     /* Loop until we see the split happen in HID0 */
0060 1:  mfspr   r4, SPRN_HID0
0061     and.    r4, r4, r5
0062     beq 1b
0063
0064     /*
0065      * We only need to initialise the below regs once for each subcore,
0066      * but it's simpler and harmless to do it on each thread.
0067      */
0068
0069     /* Make sure various SPRS have sane values */
0070     li  r4, 0
0071     mtspr   SPRN_LPID, r4
0072     mtspr   SPRN_PCR, r4
0073     mtspr   SPRN_HDEC, r4
0074
0075     /* Restore SPR values now we are split */
0076     mtspr   SPRN_LDBAR, r6
0077     mtspr   SPRN_PMMAR, r7
0078     mtspr   SPRN_PMCR, r8
0079     mtspr   SPRN_RPR, r9
0080     mtspr   SPRN_SDR1, r10
0081
0082     LOAD_REG_ADDR(r5, virtual_mode)
0083
0084     /* Get out of real mode */
0085     mtspr   SPRN_SRR0,r5
0086     mtspr   SPRN_SRR1,r12
0087     rfid
0088     b   .   /* prevent speculative execution */
0089
0090 virtual_mode:
0091     blr