platforms/powernv/pci-cxl.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2014-2016 IBM Corp.
0004  */
0005
0006 #include <linux/module.h>
0007 #include <misc/cxl-base.h>
0008 #include <asm/pnv-pci.h>
0009 #include <asm/opal.h>
0010
0011 #include "pci.h"
0012
0013 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
0014 {
0015     struct pci_controller *hose = pci_bus_to_host(dev->bus);
0016     struct pnv_phb *phb = hose->private_data;
0017     struct pnv_ioda_pe *pe;
0018     int rc;
0019
0020     pe = pnv_ioda_get_pe(dev);
0021     if (!pe)
0022         return -ENODEV;
0023
0024     pe_info(pe, "Switching PHB to CXL\n");
0025
0026     rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
0027     if (rc == OPAL_UNSUPPORTED)
0028         dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n");
0029     else if (rc)
0030         dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
0031
0032     return rc;
0033 }
0034 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
0035
0036 /* Find PHB for cxl dev and allocate MSI hwirqs?
0037  * Returns the absolute hardware IRQ number
0038  */
0039 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
0040 {
0041     struct pci_controller *hose = pci_bus_to_host(dev->bus);
0042     struct pnv_phb *phb = hose->private_data;
0043     int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
0044
0045     if (hwirq < 0) {
0046         dev_warn(&dev->dev, "Failed to find a free MSI\n");
0047         return -ENOSPC;
0048     }
0049
0050     return phb->msi_base + hwirq;
0051 }
0052 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
0053
0054 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
0055 {
0056     struct pci_controller *hose = pci_bus_to_host(dev->bus);
0057     struct pnv_phb *phb = hose->private_data;
0058
0059     msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
0060 }
0061 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
0062
0063 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
0064                   struct pci_dev *dev)
0065 {
0066     struct pci_controller *hose = pci_bus_to_host(dev->bus);
0067     struct pnv_phb *phb = hose->private_data;
0068     int i, hwirq;
0069
0070     for (i = 1; i < CXL_IRQ_RANGES; i++) {
0071         if (!irqs->range[i])
0072             continue;
0073         pr_devel("cxl release irq range 0x%x: offset: 0x%lx  limit: %ld\n",
0074              i, irqs->offset[i],
0075              irqs->range[i]);
0076         hwirq = irqs->offset[i] - phb->msi_base;
0077         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
0078                        irqs->range[i]);
0079     }
0080 }
0081 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
0082
0083 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
0084                    struct pci_dev *dev, int num)
0085 {
0086     struct pci_controller *hose = pci_bus_to_host(dev->bus);
0087     struct pnv_phb *phb = hose->private_data;
0088     int i, hwirq, try;
0089
0090     memset(irqs, 0, sizeof(struct cxl_irq_ranges));
0091
0092     /* 0 is reserved for the multiplexed PSL DSI interrupt */
0093     for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
0094         try = num;
0095         while (try) {
0096             hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
0097             if (hwirq >= 0)
0098                 break;
0099             try /= 2;
0100         }
0101         if (!try)
0102             goto fail;
0103
0104         irqs->offset[i] = phb->msi_base + hwirq;
0105         irqs->range[i] = try;
0106         pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx  limit: %li\n",
0107              i, irqs->offset[i], irqs->range[i]);
0108         num -= try;
0109     }
0110     if (num)
0111         goto fail;
0112
0113     return 0;
0114 fail:
0115     pnv_cxl_release_hwirq_ranges(irqs, dev);
0116     return -ENOSPC;
0117 }
0118 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
0119
0120 int pnv_cxl_get_irq_count(struct pci_dev *dev)
0121 {
0122     struct pci_controller *hose = pci_bus_to_host(dev->bus);
0123     struct pnv_phb *phb = hose->private_data;
0124
0125     return phb->msi_bmp.irq_count;
0126 }
0127 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
0128
0129 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
0130                unsigned int virq)
0131 {
0132     struct pci_controller *hose = pci_bus_to_host(dev->bus);
0133     struct pnv_phb *phb = hose->private_data;
0134     unsigned int xive_num = hwirq - phb->msi_base;
0135     struct pnv_ioda_pe *pe;
0136     int rc;
0137
0138     if (!(pe = pnv_ioda_get_pe(dev)))
0139         return -ENODEV;
0140
0141     /* Assign XIVE to PE */
0142     rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
0143     if (rc) {
0144         pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
0145             "hwirq 0x%x XIVE 0x%x PE\n",
0146             pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
0147         return -EIO;
0148     }
0149     pnv_set_msi_irq_chip(phb, virq);
0150
0151     return 0;
0152 }
0153 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);