platforms/powernv/opal-lpc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * PowerNV LPC bus handling.
0004  *
0005  * Copyright 2013 IBM Corp.
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/of.h>
0010 #include <linux/bug.h>
0011 #include <linux/io.h>
0012 #include <linux/slab.h>
0013 #include <linux/debugfs.h>
0014
0015 #include <asm/machdep.h>
0016 #include <asm/firmware.h>
0017 #include <asm/opal.h>
0018 #include <asm/prom.h>
0019 #include <linux/uaccess.h>
0020 #include <asm/isa-bridge.h>
0021
0022 static int opal_lpc_chip_id = -1;
0023
0024 static u8 opal_lpc_inb(unsigned long port)
0025 {
0026     int64_t rc;
0027     __be32 data;
0028
0029     if (opal_lpc_chip_id < 0 || port > 0xffff)
0030         return 0xff;
0031     rc = opal_lpc_read(opal_lpc_chip_id, OPAL_LPC_IO, port, &data, 1);
0032     return rc ? 0xff : be32_to_cpu(data);
0033 }
0034
0035 static __le16 __opal_lpc_inw(unsigned long port)
0036 {
0037     int64_t rc;
0038     __be32 data;
0039
0040     if (opal_lpc_chip_id < 0 || port > 0xfffe)
0041         return 0xffff;
0042     if (port & 1)
0043         return (__le16)opal_lpc_inb(port) << 8 | opal_lpc_inb(port + 1);
0044     rc = opal_lpc_read(opal_lpc_chip_id, OPAL_LPC_IO, port, &data, 2);
0045     return rc ? 0xffff : be32_to_cpu(data);
0046 }
0047 static u16 opal_lpc_inw(unsigned long port)
0048 {
0049     return le16_to_cpu(__opal_lpc_inw(port));
0050 }
0051
0052 static __le32 __opal_lpc_inl(unsigned long port)
0053 {
0054     int64_t rc;
0055     __be32 data;
0056
0057     if (opal_lpc_chip_id < 0 || port > 0xfffc)
0058         return 0xffffffff;
0059     if (port & 3)
0060         return (__le32)opal_lpc_inb(port    ) << 24 |
0061                (__le32)opal_lpc_inb(port + 1) << 16 |
0062                (__le32)opal_lpc_inb(port + 2) <<  8 |
0063                    opal_lpc_inb(port + 3);
0064     rc = opal_lpc_read(opal_lpc_chip_id, OPAL_LPC_IO, port, &data, 4);
0065     return rc ? 0xffffffff : be32_to_cpu(data);
0066 }
0067
0068 static u32 opal_lpc_inl(unsigned long port)
0069 {
0070     return le32_to_cpu(__opal_lpc_inl(port));
0071 }
0072
0073 static void opal_lpc_outb(u8 val, unsigned long port)
0074 {
0075     if (opal_lpc_chip_id < 0 || port > 0xffff)
0076         return;
0077     opal_lpc_write(opal_lpc_chip_id, OPAL_LPC_IO, port, val, 1);
0078 }
0079
0080 static void __opal_lpc_outw(__le16 val, unsigned long port)
0081 {
0082     if (opal_lpc_chip_id < 0 || port > 0xfffe)
0083         return;
0084     if (port & 1) {
0085         opal_lpc_outb(val >> 8, port);
0086         opal_lpc_outb(val     , port + 1);
0087         return;
0088     }
0089     opal_lpc_write(opal_lpc_chip_id, OPAL_LPC_IO, port, val, 2);
0090 }
0091
0092 static void opal_lpc_outw(u16 val, unsigned long port)
0093 {
0094     __opal_lpc_outw(cpu_to_le16(val), port);
0095 }
0096
0097 static void __opal_lpc_outl(__le32 val, unsigned long port)
0098 {
0099     if (opal_lpc_chip_id < 0 || port > 0xfffc)
0100         return;
0101     if (port & 3) {
0102         opal_lpc_outb(val >> 24, port);
0103         opal_lpc_outb(val >> 16, port + 1);
0104         opal_lpc_outb(val >>  8, port + 2);
0105         opal_lpc_outb(val      , port + 3);
0106         return;
0107     }
0108     opal_lpc_write(opal_lpc_chip_id, OPAL_LPC_IO, port, val, 4);
0109 }
0110
0111 static void opal_lpc_outl(u32 val, unsigned long port)
0112 {
0113     __opal_lpc_outl(cpu_to_le32(val), port);
0114 }
0115
0116 static void opal_lpc_insb(unsigned long p, void *b, unsigned long c)
0117 {
0118     u8 *ptr = b;
0119
0120     while(c--)
0121         *(ptr++) = opal_lpc_inb(p);
0122 }
0123
0124 static void opal_lpc_insw(unsigned long p, void *b, unsigned long c)
0125 {
0126     __le16 *ptr = b;
0127
0128     while(c--)
0129         *(ptr++) = __opal_lpc_inw(p);
0130 }
0131
0132 static void opal_lpc_insl(unsigned long p, void *b, unsigned long c)
0133 {
0134     __le32 *ptr = b;
0135
0136     while(c--)
0137         *(ptr++) = __opal_lpc_inl(p);
0138 }
0139
0140 static void opal_lpc_outsb(unsigned long p, const void *b, unsigned long c)
0141 {
0142     const u8 *ptr = b;
0143
0144     while(c--)
0145         opal_lpc_outb(*(ptr++), p);
0146 }
0147
0148 static void opal_lpc_outsw(unsigned long p, const void *b, unsigned long c)
0149 {
0150     const __le16 *ptr = b;
0151
0152     while(c--)
0153         __opal_lpc_outw(*(ptr++), p);
0154 }
0155
0156 static void opal_lpc_outsl(unsigned long p, const void *b, unsigned long c)
0157 {
0158     const __le32 *ptr = b;
0159
0160     while(c--)
0161         __opal_lpc_outl(*(ptr++), p);
0162 }
0163
0164 static const struct ppc_pci_io opal_lpc_io = {
0165     .inb    = opal_lpc_inb,
0166     .inw    = opal_lpc_inw,
0167     .inl    = opal_lpc_inl,
0168     .outb   = opal_lpc_outb,
0169     .outw   = opal_lpc_outw,
0170     .outl   = opal_lpc_outl,
0171     .insb   = opal_lpc_insb,
0172     .insw   = opal_lpc_insw,
0173     .insl   = opal_lpc_insl,
0174     .outsb  = opal_lpc_outsb,
0175     .outsw  = opal_lpc_outsw,
0176     .outsl  = opal_lpc_outsl,
0177 };
0178
0179 #ifdef CONFIG_DEBUG_FS
0180 struct lpc_debugfs_entry {
0181     enum OpalLPCAddressType lpc_type;
0182 };
0183
0184 static ssize_t lpc_debug_read(struct file *filp, char __user *ubuf,
0185                   size_t count, loff_t *ppos)
0186 {
0187     struct lpc_debugfs_entry *lpc = filp->private_data;
0188     u32 data, pos, len, todo;
0189     int rc;
0190
0191     if (!access_ok(ubuf, count))
0192         return -EFAULT;
0193
0194     todo = count;
0195     while (todo) {
0196         pos = *ppos;
0197
0198         /*
0199          * Select access size based on count and alignment and
0200          * access type. IO and MEM only support byte accesses,
0201          * FW supports all 3.
0202          */
0203         len = 1;
0204         if (lpc->lpc_type == OPAL_LPC_FW) {
0205             if (todo > 3 && (pos & 3) == 0)
0206                 len = 4;
0207             else if (todo > 1 && (pos & 1) == 0)
0208                 len = 2;
0209         }
0210         rc = opal_lpc_read(opal_lpc_chip_id, lpc->lpc_type, pos,
0211                    &data, len);
0212         if (rc)
0213             return -ENXIO;
0214
0215         /*
0216          * Now there is some trickery with the data returned by OPAL
0217          * as it's the desired data right justified in a 32-bit BE
0218          * word.
0219          *
0220          * This is a very bad interface and I'm to blame for it :-(
0221          *
0222          * So we can't just apply a 32-bit swap to what comes from OPAL,
0223          * because user space expects the *bytes* to be in their proper
0224          * respective positions (ie, LPC position).
0225          *
0226          * So what we really want to do here is to shift data right
0227          * appropriately on a LE kernel.
0228          *
0229          * IE. If the LPC transaction has bytes B0, B1, B2 and B3 in that
0230          * order, we have in memory written to by OPAL at the "data"
0231          * pointer:
0232          *
0233          *               Bytes:      OPAL "data"   LE "data"
0234          *   32-bit:   B0 B1 B2 B3   B0B1B2B3      B3B2B1B0
0235          *   16-bit:   B0 B1         0000B0B1      B1B00000
0236          *    8-bit:   B0            000000B0      B0000000
0237          *
0238          * So a BE kernel will have the leftmost of the above in the MSB
0239          * and rightmost in the LSB and can just then "cast" the u32 "data"
0240          * down to the appropriate quantity and write it.
0241          *
0242          * However, an LE kernel can't. It doesn't need to swap because a
0243          * load from data followed by a store to user are going to preserve
0244          * the byte ordering which is the wire byte order which is what the
0245          * user wants, but in order to "crop" to the right size, we need to
0246          * shift right first.
0247          */
0248         switch(len) {
0249         case 4:
0250             rc = __put_user((u32)data, (u32 __user *)ubuf);
0251             break;
0252         case 2:
0253 #ifdef __LITTLE_ENDIAN__
0254             data >>= 16;
0255 #endif
0256             rc = __put_user((u16)data, (u16 __user *)ubuf);
0257             break;
0258         default:
0259 #ifdef __LITTLE_ENDIAN__
0260             data >>= 24;
0261 #endif
0262             rc = __put_user((u8)data, (u8 __user *)ubuf);
0263             break;
0264         }
0265         if (rc)
0266             return -EFAULT;
0267         *ppos += len;
0268         ubuf += len;
0269         todo -= len;
0270     }
0271
0272     return count;
0273 }
0274
0275 static ssize_t lpc_debug_write(struct file *filp, const char __user *ubuf,
0276                    size_t count, loff_t *ppos)
0277 {
0278     struct lpc_debugfs_entry *lpc = filp->private_data;
0279     u32 data, pos, len, todo;
0280     int rc;
0281
0282     if (!access_ok(ubuf, count))
0283         return -EFAULT;
0284
0285     todo = count;
0286     while (todo) {
0287         pos = *ppos;
0288
0289         /*
0290          * Select access size based on count and alignment and
0291          * access type. IO and MEM only support byte acceses,
0292          * FW supports all 3.
0293          */
0294         len = 1;
0295         if (lpc->lpc_type == OPAL_LPC_FW) {
0296             if (todo > 3 && (pos & 3) == 0)
0297                 len = 4;
0298             else if (todo > 1 && (pos & 1) == 0)
0299                 len = 2;
0300         }
0301
0302         /*
0303          * Similarly to the read case, we have some trickery here but
0304          * it's different to handle. We need to pass the value to OPAL in
0305          * a register whose layout depends on the access size. We want
0306          * to reproduce the memory layout of the user, however we aren't
0307          * doing a load from user and a store to another memory location
0308          * which would achieve that. Here we pass the value to OPAL via
0309          * a register which is expected to contain the "BE" interpretation
0310          * of the byte sequence. IE: for a 32-bit access, byte 0 should be
0311          * in the MSB. So here we *do* need to byteswap on LE.
0312          *
0313          *           User bytes:    LE "data"  OPAL "data"
0314          *  32-bit:  B0 B1 B2 B3    B3B2B1B0   B0B1B2B3
0315          *  16-bit:  B0 B1          0000B1B0   0000B0B1
0316          *   8-bit:  B0             000000B0   000000B0
0317          */
0318         switch(len) {
0319         case 4:
0320             rc = __get_user(data, (u32 __user *)ubuf);
0321             data = cpu_to_be32(data);
0322             break;
0323         case 2:
0324             rc = __get_user(data, (u16 __user *)ubuf);
0325             data = cpu_to_be16(data);
0326             break;
0327         default:
0328             rc = __get_user(data, (u8 __user *)ubuf);
0329             break;
0330         }
0331         if (rc)
0332             return -EFAULT;
0333
0334         rc = opal_lpc_write(opal_lpc_chip_id, lpc->lpc_type, pos,
0335                     data, len);
0336         if (rc)
0337             return -ENXIO;
0338         *ppos += len;
0339         ubuf += len;
0340         todo -= len;
0341     }
0342
0343     return count;
0344 }
0345
0346 static const struct file_operations lpc_fops = {
0347     .read =     lpc_debug_read,
0348     .write =    lpc_debug_write,
0349     .open =     simple_open,
0350     .llseek =   default_llseek,
0351 };
0352
0353 static int opal_lpc_debugfs_create_type(struct dentry *folder,
0354                     const char *fname,
0355                     enum OpalLPCAddressType type)
0356 {
0357     struct lpc_debugfs_entry *entry;
0358     entry = kzalloc(sizeof(*entry), GFP_KERNEL);
0359     if (!entry)
0360         return -ENOMEM;
0361     entry->lpc_type = type;
0362     debugfs_create_file(fname, 0600, folder, entry, &lpc_fops);
0363     return 0;
0364 }
0365
0366 static int opal_lpc_init_debugfs(void)
0367 {
0368     struct dentry *root;
0369     int rc = 0;
0370
0371     if (opal_lpc_chip_id < 0)
0372         return -ENODEV;
0373
0374     root = debugfs_create_dir("lpc", arch_debugfs_dir);
0375
0376     rc |= opal_lpc_debugfs_create_type(root, "io", OPAL_LPC_IO);
0377     rc |= opal_lpc_debugfs_create_type(root, "mem", OPAL_LPC_MEM);
0378     rc |= opal_lpc_debugfs_create_type(root, "fw", OPAL_LPC_FW);
0379     return rc;
0380 }
0381 machine_device_initcall(powernv, opal_lpc_init_debugfs);
0382 #endif  /* CONFIG_DEBUG_FS */
0383
0384 void __init opal_lpc_init(void)
0385 {
0386     struct device_node *np;
0387
0388     /*
0389      * Look for a Power8 LPC bus tagged as "primary",
0390      * we currently support only one though the OPAL APIs
0391      * support any number.
0392      */
0393     for_each_compatible_node(np, NULL, "ibm,power8-lpc") {
0394         if (!of_device_is_available(np))
0395             continue;
0396         if (!of_get_property(np, "primary", NULL))
0397             continue;
0398         opal_lpc_chip_id = of_get_ibm_chip_id(np);
0399         of_node_put(np);
0400         break;
0401     }
0402     if (opal_lpc_chip_id < 0)
0403         return;
0404
0405     /* Does it support direct mapping ? */
0406     if (of_get_property(np, "ranges", NULL)) {
0407         pr_info("OPAL: Found memory mapped LPC bus on chip %d\n",
0408             opal_lpc_chip_id);
0409         isa_bridge_init_non_pci(np);
0410     } else {
0411         pr_info("OPAL: Found non-mapped LPC bus on chip %d\n",
0412             opal_lpc_chip_id);
0413
0414         /* Setup special IO ops */
0415         ppc_pci_io = opal_lpc_io;
0416         isa_io_special = true;
0417     }
0418 }