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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Support for the interrupt controllers found on Power Macintosh,
0004  *  currently Apple's "Grand Central" interrupt controller in all
0005  *  it's incarnations. OpenPIC support used on newer machines is
0006  *  in a separate file
0007  *
0008  *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
0009  *  Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
0010  *                     IBM, Corp.
0011  */
0012 
0013 #include <linux/stddef.h>
0014 #include <linux/init.h>
0015 #include <linux/sched.h>
0016 #include <linux/signal.h>
0017 #include <linux/pci.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/syscore_ops.h>
0020 #include <linux/adb.h>
0021 #include <linux/minmax.h>
0022 #include <linux/pmu.h>
0023 #include <linux/irqdomain.h>
0024 #include <linux/of_address.h>
0025 #include <linux/of_irq.h>
0026 
0027 #include <asm/sections.h>
0028 #include <asm/io.h>
0029 #include <asm/smp.h>
0030 #include <asm/pci-bridge.h>
0031 #include <asm/time.h>
0032 #include <asm/pmac_feature.h>
0033 #include <asm/mpic.h>
0034 #include <asm/xmon.h>
0035 
0036 #include "pmac.h"
0037 
0038 #ifdef CONFIG_PPC32
0039 struct pmac_irq_hw {
0040         unsigned int    event;
0041         unsigned int    enable;
0042         unsigned int    ack;
0043         unsigned int    level;
0044 };
0045 
0046 /* Workaround flags for 32bit powermac machines */
0047 unsigned int of_irq_workarounds;
0048 struct device_node *of_irq_dflt_pic;
0049 
0050 /* Default addresses */
0051 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
0052 
0053 static int max_irqs;
0054 static int max_real_irqs;
0055 
0056 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
0057 
0058 /* The max irq number this driver deals with is 128; see max_irqs */
0059 static DECLARE_BITMAP(ppc_lost_interrupts, 128);
0060 static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
0061 static int pmac_irq_cascade = -1;
0062 static struct irq_domain *pmac_pic_host;
0063 
0064 static void __pmac_retrigger(unsigned int irq_nr)
0065 {
0066     if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
0067         __set_bit(irq_nr, ppc_lost_interrupts);
0068         irq_nr = pmac_irq_cascade;
0069         mb();
0070     }
0071     if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
0072         atomic_inc(&ppc_n_lost_interrupts);
0073         set_dec(1);
0074     }
0075 }
0076 
0077 static void pmac_mask_and_ack_irq(struct irq_data *d)
0078 {
0079     unsigned int src = irqd_to_hwirq(d);
0080         unsigned long bit = 1UL << (src & 0x1f);
0081         int i = src >> 5;
0082         unsigned long flags;
0083 
0084     raw_spin_lock_irqsave(&pmac_pic_lock, flags);
0085         __clear_bit(src, ppc_cached_irq_mask);
0086         if (__test_and_clear_bit(src, ppc_lost_interrupts))
0087                 atomic_dec(&ppc_n_lost_interrupts);
0088         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
0089         out_le32(&pmac_irq_hw[i]->ack, bit);
0090         do {
0091                 /* make sure ack gets to controller before we enable
0092                    interrupts */
0093                 mb();
0094         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
0095                 != (ppc_cached_irq_mask[i] & bit));
0096     raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
0097 }
0098 
0099 static void pmac_ack_irq(struct irq_data *d)
0100 {
0101     unsigned int src = irqd_to_hwirq(d);
0102         unsigned long bit = 1UL << (src & 0x1f);
0103         int i = src >> 5;
0104         unsigned long flags;
0105 
0106     raw_spin_lock_irqsave(&pmac_pic_lock, flags);
0107     if (__test_and_clear_bit(src, ppc_lost_interrupts))
0108                 atomic_dec(&ppc_n_lost_interrupts);
0109         out_le32(&pmac_irq_hw[i]->ack, bit);
0110         (void)in_le32(&pmac_irq_hw[i]->ack);
0111     raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
0112 }
0113 
0114 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
0115 {
0116         unsigned long bit = 1UL << (irq_nr & 0x1f);
0117         int i = irq_nr >> 5;
0118 
0119         if ((unsigned)irq_nr >= max_irqs)
0120                 return;
0121 
0122         /* enable unmasked interrupts */
0123         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
0124 
0125         do {
0126                 /* make sure mask gets to controller before we
0127                    return to user */
0128                 mb();
0129         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
0130                 != (ppc_cached_irq_mask[i] & bit));
0131 
0132         /*
0133          * Unfortunately, setting the bit in the enable register
0134          * when the device interrupt is already on *doesn't* set
0135          * the bit in the flag register or request another interrupt.
0136          */
0137         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
0138         __pmac_retrigger(irq_nr);
0139 }
0140 
0141 /* When an irq gets requested for the first client, if it's an
0142  * edge interrupt, we clear any previous one on the controller
0143  */
0144 static unsigned int pmac_startup_irq(struct irq_data *d)
0145 {
0146     unsigned long flags;
0147     unsigned int src = irqd_to_hwirq(d);
0148         unsigned long bit = 1UL << (src & 0x1f);
0149         int i = src >> 5;
0150 
0151     raw_spin_lock_irqsave(&pmac_pic_lock, flags);
0152     if (!irqd_is_level_type(d))
0153         out_le32(&pmac_irq_hw[i]->ack, bit);
0154         __set_bit(src, ppc_cached_irq_mask);
0155         __pmac_set_irq_mask(src, 0);
0156     raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
0157 
0158     return 0;
0159 }
0160 
0161 static void pmac_mask_irq(struct irq_data *d)
0162 {
0163     unsigned long flags;
0164     unsigned int src = irqd_to_hwirq(d);
0165 
0166     raw_spin_lock_irqsave(&pmac_pic_lock, flags);
0167         __clear_bit(src, ppc_cached_irq_mask);
0168         __pmac_set_irq_mask(src, 1);
0169     raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
0170 }
0171 
0172 static void pmac_unmask_irq(struct irq_data *d)
0173 {
0174     unsigned long flags;
0175     unsigned int src = irqd_to_hwirq(d);
0176 
0177     raw_spin_lock_irqsave(&pmac_pic_lock, flags);
0178     __set_bit(src, ppc_cached_irq_mask);
0179         __pmac_set_irq_mask(src, 0);
0180     raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
0181 }
0182 
0183 static int pmac_retrigger(struct irq_data *d)
0184 {
0185     unsigned long flags;
0186 
0187     raw_spin_lock_irqsave(&pmac_pic_lock, flags);
0188     __pmac_retrigger(irqd_to_hwirq(d));
0189     raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
0190     return 1;
0191 }
0192 
0193 static struct irq_chip pmac_pic = {
0194     .name       = "PMAC-PIC",
0195     .irq_startup    = pmac_startup_irq,
0196     .irq_mask   = pmac_mask_irq,
0197     .irq_ack    = pmac_ack_irq,
0198     .irq_mask_ack   = pmac_mask_and_ack_irq,
0199     .irq_unmask = pmac_unmask_irq,
0200     .irq_retrigger  = pmac_retrigger,
0201 };
0202 
0203 static irqreturn_t gatwick_action(int cpl, void *dev_id)
0204 {
0205     unsigned long flags;
0206     int irq, bits;
0207     int rc = IRQ_NONE;
0208 
0209     raw_spin_lock_irqsave(&pmac_pic_lock, flags);
0210     for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
0211         int i = irq >> 5;
0212         bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
0213         bits |= in_le32(&pmac_irq_hw[i]->level);
0214         bits &= ppc_cached_irq_mask[i];
0215         if (bits == 0)
0216             continue;
0217         irq += __ilog2(bits);
0218         raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
0219         generic_handle_irq(irq);
0220         raw_spin_lock_irqsave(&pmac_pic_lock, flags);
0221         rc = IRQ_HANDLED;
0222     }
0223     raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
0224     return rc;
0225 }
0226 
0227 static unsigned int pmac_pic_get_irq(void)
0228 {
0229     int irq;
0230     unsigned long bits = 0;
0231     unsigned long flags;
0232 
0233 #ifdef CONFIG_PPC_PMAC32_PSURGE
0234     /* IPI's are a hack on the powersurge -- Cort */
0235     if (smp_processor_id() != 0) {
0236         return  psurge_secondary_virq;
0237         }
0238 #endif /* CONFIG_PPC_PMAC32_PSURGE */
0239     raw_spin_lock_irqsave(&pmac_pic_lock, flags);
0240     for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
0241         int i = irq >> 5;
0242         bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
0243         bits |= in_le32(&pmac_irq_hw[i]->level);
0244         bits &= ppc_cached_irq_mask[i];
0245         if (bits == 0)
0246             continue;
0247         irq += __ilog2(bits);
0248         break;
0249     }
0250     raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
0251     if (unlikely(irq < 0))
0252         return 0;
0253     return irq_linear_revmap(pmac_pic_host, irq);
0254 }
0255 
0256 static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node,
0257                    enum irq_domain_bus_token bus_token)
0258 {
0259     /* We match all, we don't always have a node anyway */
0260     return 1;
0261 }
0262 
0263 static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
0264                  irq_hw_number_t hw)
0265 {
0266     if (hw >= max_irqs)
0267         return -EINVAL;
0268 
0269     /* Mark level interrupts, set delayed disable for edge ones and set
0270      * handlers
0271      */
0272     irq_set_status_flags(virq, IRQ_LEVEL);
0273     irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
0274     return 0;
0275 }
0276 
0277 static const struct irq_domain_ops pmac_pic_host_ops = {
0278     .match = pmac_pic_host_match,
0279     .map = pmac_pic_host_map,
0280     .xlate = irq_domain_xlate_onecell,
0281 };
0282 
0283 static void __init pmac_pic_probe_oldstyle(void)
0284 {
0285         int i;
0286         struct device_node *master = NULL;
0287     struct device_node *slave = NULL;
0288     u8 __iomem *addr;
0289     struct resource r;
0290 
0291     /* Set our get_irq function */
0292     ppc_md.get_irq = pmac_pic_get_irq;
0293 
0294     /*
0295      * Find the interrupt controller type & node
0296      */
0297 
0298     if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
0299         max_irqs = max_real_irqs = 32;
0300     } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
0301         max_irqs = max_real_irqs = 32;
0302         /* We might have a second cascaded ohare */
0303         slave = of_find_node_by_name(NULL, "pci106b,7");
0304         if (slave)
0305             max_irqs = 64;
0306     } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
0307         max_irqs = max_real_irqs = 64;
0308 
0309         /* We might have a second cascaded heathrow */
0310 
0311         /* Compensate for of_node_put() in of_find_node_by_name() */
0312         of_node_get(master);
0313         slave = of_find_node_by_name(master, "mac-io");
0314 
0315         /* Check ordering of master & slave */
0316         if (of_device_is_compatible(master, "gatwick")) {
0317             BUG_ON(slave == NULL);
0318             swap(master, slave);
0319         }
0320 
0321         /* We found a slave */
0322         if (slave)
0323             max_irqs = 128;
0324     }
0325     BUG_ON(master == NULL);
0326 
0327     /*
0328      * Allocate an irq host
0329      */
0330     pmac_pic_host = irq_domain_add_linear(master, max_irqs,
0331                           &pmac_pic_host_ops, NULL);
0332     BUG_ON(pmac_pic_host == NULL);
0333     irq_set_default_host(pmac_pic_host);
0334 
0335     /* Get addresses of first controller if we have a node for it */
0336     BUG_ON(of_address_to_resource(master, 0, &r));
0337 
0338     /* Map interrupts of primary controller */
0339     addr = (u8 __iomem *) ioremap(r.start, 0x40);
0340     i = 0;
0341     pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
0342         (addr + 0x20);
0343     if (max_real_irqs > 32)
0344         pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
0345             (addr + 0x10);
0346     of_node_put(master);
0347 
0348     printk(KERN_INFO "irq: Found primary Apple PIC %pOF for %d irqs\n",
0349            master, max_real_irqs);
0350 
0351     /* Map interrupts of cascaded controller */
0352     if (slave && !of_address_to_resource(slave, 0, &r)) {
0353         addr = (u8 __iomem *)ioremap(r.start, 0x40);
0354         pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
0355             (addr + 0x20);
0356         if (max_irqs > 64)
0357             pmac_irq_hw[i++] =
0358                 (volatile struct pmac_irq_hw __iomem *)
0359                 (addr + 0x10);
0360         pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
0361 
0362         printk(KERN_INFO "irq: Found slave Apple PIC %pOF for %d irqs"
0363                " cascade: %d\n", slave,
0364                max_irqs - max_real_irqs, pmac_irq_cascade);
0365     }
0366     of_node_put(slave);
0367 
0368     /* Disable all interrupts in all controllers */
0369     for (i = 0; i * 32 < max_irqs; ++i)
0370         out_le32(&pmac_irq_hw[i]->enable, 0);
0371 
0372     /* Hookup cascade irq */
0373     if (slave && pmac_irq_cascade) {
0374         if (request_irq(pmac_irq_cascade, gatwick_action,
0375                 IRQF_NO_THREAD, "cascade", NULL))
0376             pr_err("Failed to register cascade interrupt\n");
0377     }
0378 
0379     printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
0380 #ifdef CONFIG_XMON
0381     i = irq_create_mapping(NULL, 20);
0382     if (request_irq(i, xmon_irq, IRQF_NO_THREAD, "NMI - XMON", NULL))
0383         pr_err("Failed to register NMI-XMON interrupt\n");
0384 #endif
0385 }
0386 
0387 int of_irq_parse_oldworld(const struct device_node *device, int index,
0388             struct of_phandle_args *out_irq)
0389 {
0390     const u32 *ints = NULL;
0391     int intlen;
0392 
0393     /*
0394      * Old machines just have a list of interrupt numbers
0395      * and no interrupt-controller nodes. We also have dodgy
0396      * cases where the APPL,interrupts property is completely
0397      * missing behind pci-pci bridges and we have to get it
0398      * from the parent (the bridge itself, as apple just wired
0399      * everything together on these)
0400      */
0401     while (device) {
0402         ints = of_get_property(device, "AAPL,interrupts", &intlen);
0403         if (ints != NULL)
0404             break;
0405         device = device->parent;
0406         if (!of_node_is_type(device, "pci"))
0407             break;
0408     }
0409     if (ints == NULL)
0410         return -EINVAL;
0411     intlen /= sizeof(u32);
0412 
0413     if (index >= intlen)
0414         return -EINVAL;
0415 
0416     out_irq->np = NULL;
0417     out_irq->args[0] = ints[index];
0418     out_irq->args_count = 1;
0419 
0420     return 0;
0421 }
0422 #endif /* CONFIG_PPC32 */
0423 
0424 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
0425 {
0426 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
0427     struct device_node* pswitch;
0428     int nmi_irq;
0429 
0430     pswitch = of_find_node_by_name(NULL, "programmer-switch");
0431     if (pswitch) {
0432         nmi_irq = irq_of_parse_and_map(pswitch, 0);
0433         if (nmi_irq) {
0434             mpic_irq_set_priority(nmi_irq, 9);
0435             if (request_irq(nmi_irq, xmon_irq, IRQF_NO_THREAD,
0436                     "NMI - XMON", NULL))
0437                 pr_err("Failed to register NMI-XMON interrupt\n");
0438         }
0439         of_node_put(pswitch);
0440     }
0441 #endif  /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
0442 }
0443 
0444 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
0445                         int master)
0446 {
0447     const char *name = master ? " MPIC 1   " : " MPIC 2   ";
0448     struct mpic *mpic;
0449     unsigned int flags = master ? 0 : MPIC_SECONDARY;
0450 
0451     pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
0452 
0453     if (of_get_property(np, "big-endian", NULL))
0454         flags |= MPIC_BIG_ENDIAN;
0455 
0456     /* Primary Big Endian means HT interrupts. This is quite dodgy
0457      * but works until I find a better way
0458      */
0459     if (master && (flags & MPIC_BIG_ENDIAN))
0460         flags |= MPIC_U3_HT_IRQS;
0461 
0462     mpic = mpic_alloc(np, 0, flags, 0, 0, name);
0463     if (mpic == NULL)
0464         return NULL;
0465 
0466     mpic_init(mpic);
0467 
0468     return mpic;
0469  }
0470 
0471 static int __init pmac_pic_probe_mpic(void)
0472 {
0473     struct mpic *mpic1, *mpic2;
0474     struct device_node *np, *master = NULL, *slave = NULL;
0475 
0476     /* We can have up to 2 MPICs cascaded */
0477     for_each_node_by_type(np, "open-pic") {
0478         if (master == NULL &&
0479             of_get_property(np, "interrupts", NULL) == NULL)
0480             master = of_node_get(np);
0481         else if (slave == NULL)
0482             slave = of_node_get(np);
0483         if (master && slave) {
0484             of_node_put(np);
0485             break;
0486         }
0487     }
0488 
0489     /* Check for bogus setups */
0490     if (master == NULL && slave != NULL) {
0491         master = slave;
0492         slave = NULL;
0493     }
0494 
0495     /* Not found, default to good old pmac pic */
0496     if (master == NULL)
0497         return -ENODEV;
0498 
0499     /* Set master handler */
0500     ppc_md.get_irq = mpic_get_irq;
0501 
0502     /* Setup master */
0503     mpic1 = pmac_setup_one_mpic(master, 1);
0504     BUG_ON(mpic1 == NULL);
0505 
0506     /* Install NMI if any */
0507     pmac_pic_setup_mpic_nmi(mpic1);
0508 
0509     of_node_put(master);
0510 
0511     /* Set up a cascaded controller, if present */
0512     if (slave) {
0513         mpic2 = pmac_setup_one_mpic(slave, 0);
0514         if (mpic2 == NULL)
0515             printk(KERN_ERR "Failed to setup slave MPIC\n");
0516         of_node_put(slave);
0517     }
0518 
0519     return 0;
0520 }
0521 
0522 
0523 void __init pmac_pic_init(void)
0524 {
0525     /* We configure the OF parsing based on our oldworld vs. newworld
0526      * platform type and whether we were booted by BootX.
0527      */
0528 #ifdef CONFIG_PPC32
0529     if (!pmac_newworld)
0530         of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
0531     if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
0532         of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
0533 
0534     /* If we don't have phandles on a newworld, then try to locate a
0535      * default interrupt controller (happens when booting with BootX).
0536      * We do a first match here, hopefully, that only ever happens on
0537      * machines with one controller.
0538      */
0539     if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
0540         struct device_node *np;
0541 
0542         for_each_node_with_property(np, "interrupt-controller") {
0543             /* Skip /chosen/interrupt-controller */
0544             if (of_node_name_eq(np, "chosen"))
0545                 continue;
0546             /* It seems like at least one person wants
0547              * to use BootX on a machine with an AppleKiwi
0548              * controller which happens to pretend to be an
0549              * interrupt controller too. */
0550             if (of_node_name_eq(np, "AppleKiwi"))
0551                 continue;
0552             /* I think we found one ! */
0553             of_irq_dflt_pic = np;
0554             break;
0555         }
0556     }
0557 #endif /* CONFIG_PPC32 */
0558 
0559     /* We first try to detect Apple's new Core99 chipset, since mac-io
0560      * is quite different on those machines and contains an IBM MPIC2.
0561      */
0562     if (pmac_pic_probe_mpic() == 0)
0563         return;
0564 
0565 #ifdef CONFIG_PPC32
0566     pmac_pic_probe_oldstyle();
0567 #endif
0568 }
0569 
0570 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
0571 /*
0572  * These procedures are used in implementing sleep on the powerbooks.
0573  * sleep_save_intrs() saves the states of all interrupt enables
0574  * and disables all interrupts except for the nominated one.
0575  * sleep_restore_intrs() restores the states of all interrupt enables.
0576  */
0577 unsigned long sleep_save_mask[2];
0578 
0579 /* This used to be passed by the PMU driver but that link got
0580  * broken with the new driver model. We use this tweak for now...
0581  * We really want to do things differently though...
0582  */
0583 static int pmacpic_find_viaint(void)
0584 {
0585     int viaint = -1;
0586 
0587 #ifdef CONFIG_ADB_PMU
0588     struct device_node *np;
0589 
0590     if (pmu_get_model() != PMU_OHARE_BASED)
0591         goto not_found;
0592     np = of_find_node_by_name(NULL, "via-pmu");
0593     if (np == NULL)
0594         goto not_found;
0595     viaint = irq_of_parse_and_map(np, 0);
0596     of_node_put(np);
0597 
0598 not_found:
0599 #endif /* CONFIG_ADB_PMU */
0600     return viaint;
0601 }
0602 
0603 static int pmacpic_suspend(void)
0604 {
0605     int viaint = pmacpic_find_viaint();
0606 
0607     sleep_save_mask[0] = ppc_cached_irq_mask[0];
0608     sleep_save_mask[1] = ppc_cached_irq_mask[1];
0609     ppc_cached_irq_mask[0] = 0;
0610     ppc_cached_irq_mask[1] = 0;
0611     if (viaint > 0)
0612         set_bit(viaint, ppc_cached_irq_mask);
0613     out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
0614     if (max_real_irqs > 32)
0615         out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
0616     (void)in_le32(&pmac_irq_hw[0]->event);
0617     /* make sure mask gets to controller before we return to caller */
0618     mb();
0619         (void)in_le32(&pmac_irq_hw[0]->enable);
0620 
0621         return 0;
0622 }
0623 
0624 static void pmacpic_resume(void)
0625 {
0626     int i;
0627 
0628     out_le32(&pmac_irq_hw[0]->enable, 0);
0629     if (max_real_irqs > 32)
0630         out_le32(&pmac_irq_hw[1]->enable, 0);
0631     mb();
0632     for (i = 0; i < max_real_irqs; ++i)
0633         if (test_bit(i, sleep_save_mask))
0634             pmac_unmask_irq(irq_get_irq_data(i));
0635 }
0636 
0637 static struct syscore_ops pmacpic_syscore_ops = {
0638     .suspend    = pmacpic_suspend,
0639     .resume     = pmacpic_resume,
0640 };
0641 
0642 static int __init init_pmacpic_syscore(void)
0643 {
0644     if (pmac_irq_hw[0])
0645         register_syscore_ops(&pmacpic_syscore_ops);
0646     return 0;
0647 }
0648 
0649 machine_subsys_initcall(powermac, init_pmacpic_syscore);
0650 
0651 #endif /* CONFIG_PM && CONFIG_PPC32 */
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