platforms/powermac/pfunc_base.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/types.h>
0003 #include <linux/init.h>
0004 #include <linux/delay.h>
0005 #include <linux/kernel.h>
0006 #include <linux/interrupt.h>
0007 #include <linux/spinlock.h>
0008 #include <linux/of_irq.h>
0009
0010 #include <asm/pmac_feature.h>
0011 #include <asm/pmac_pfunc.h>
0012
0013 #undef DEBUG
0014 #ifdef DEBUG
0015 #define DBG(fmt...) printk(fmt)
0016 #else
0017 #define DBG(fmt...)
0018 #endif
0019
0020 static irqreturn_t macio_gpio_irq(int irq, void *data)
0021 {
0022     pmf_do_irq(data);
0023
0024     return IRQ_HANDLED;
0025 }
0026
0027 static int macio_do_gpio_irq_enable(struct pmf_function *func)
0028 {
0029     unsigned int irq = irq_of_parse_and_map(func->node, 0);
0030     if (!irq)
0031         return -EINVAL;
0032     return request_irq(irq, macio_gpio_irq, 0, func->node->name, func);
0033 }
0034
0035 static int macio_do_gpio_irq_disable(struct pmf_function *func)
0036 {
0037     unsigned int irq = irq_of_parse_and_map(func->node, 0);
0038     if (!irq)
0039         return -EINVAL;
0040     free_irq(irq, func);
0041     return 0;
0042 }
0043
0044 static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask)
0045 {
0046     u8 __iomem *addr = (u8 __iomem *)func->driver_data;
0047     unsigned long flags;
0048     u8 tmp;
0049
0050     /* Check polarity */
0051     if (args && args->count && !args->u[0].v)
0052         value = ~value;
0053
0054     /* Toggle the GPIO */
0055     raw_spin_lock_irqsave(&feature_lock, flags);
0056     tmp = readb(addr);
0057     tmp = (tmp & ~mask) | (value & mask);
0058     DBG("Do write 0x%02x to GPIO %pOF (%p)\n",
0059         tmp, func->node, addr);
0060     writeb(tmp, addr);
0061     raw_spin_unlock_irqrestore(&feature_lock, flags);
0062
0063     return 0;
0064 }
0065
0066 static int macio_do_gpio_read(PMF_STD_ARGS, u8 mask, int rshift, u8 xor)
0067 {
0068     u8 __iomem *addr = (u8 __iomem *)func->driver_data;
0069     u32 value;
0070
0071     /* Check if we have room for reply */
0072     if (args == NULL || args->count == 0 || args->u[0].p == NULL)
0073         return -EINVAL;
0074
0075     value = readb(addr);
0076     *args->u[0].p = ((value & mask) >> rshift) ^ xor;
0077
0078     return 0;
0079 }
0080
0081 static int macio_do_delay(PMF_STD_ARGS, u32 duration)
0082 {
0083     /* assume we can sleep ! */
0084     msleep((duration + 999) / 1000);
0085     return 0;
0086 }
0087
0088 static struct pmf_handlers macio_gpio_handlers = {
0089     .irq_enable = macio_do_gpio_irq_enable,
0090     .irq_disable    = macio_do_gpio_irq_disable,
0091     .write_gpio = macio_do_gpio_write,
0092     .read_gpio  = macio_do_gpio_read,
0093     .delay      = macio_do_delay,
0094 };
0095
0096 static void __init macio_gpio_init_one(struct macio_chip *macio)
0097 {
0098     struct device_node *gparent, *gp;
0099
0100     /*
0101      * Find the "gpio" parent node
0102      */
0103
0104     for_each_child_of_node(macio->of_node, gparent)
0105         if (of_node_name_eq(gparent, "gpio"))
0106             break;
0107     if (gparent == NULL)
0108         return;
0109
0110     DBG("Installing GPIO functions for macio %pOF\n",
0111         macio->of_node);
0112
0113     /*
0114      * Ok, got one, we dont need anything special to track them down, so
0115      * we just create them all
0116      */
0117     for_each_child_of_node(gparent, gp) {
0118         const u32 *reg = of_get_property(gp, "reg", NULL);
0119         unsigned long offset;
0120         if (reg == NULL)
0121             continue;
0122         offset = *reg;
0123         /* Deal with old style device-tree. We can safely hard code the
0124          * offset for now too even if it's a bit gross ...
0125          */
0126         if (offset < 0x50)
0127             offset += 0x50;
0128         offset += (unsigned long)macio->base;
0129         pmf_register_driver(gp, &macio_gpio_handlers, (void *)offset);
0130     }
0131
0132     DBG("Calling initial GPIO functions for macio %pOF\n",
0133         macio->of_node);
0134
0135     /* And now we run all the init ones */
0136     for_each_child_of_node(gparent, gp)
0137         pmf_do_functions(gp, NULL, 0, PMF_FLAGS_ON_INIT, NULL);
0138
0139     /* Note: We do not at this point implement the "at sleep" or "at wake"
0140      * functions. I yet to find any for GPIOs anyway
0141      */
0142 }
0143
0144 static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
0145 {
0146     struct macio_chip *macio = func->driver_data;
0147     unsigned long flags;
0148
0149     raw_spin_lock_irqsave(&feature_lock, flags);
0150     MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) | (value & mask));
0151     raw_spin_unlock_irqrestore(&feature_lock, flags);
0152     return 0;
0153 }
0154
0155 static int macio_do_read_reg32(PMF_STD_ARGS, u32 offset)
0156 {
0157     struct macio_chip *macio = func->driver_data;
0158
0159     /* Check if we have room for reply */
0160     if (args == NULL || args->count == 0 || args->u[0].p == NULL)
0161         return -EINVAL;
0162
0163     *args->u[0].p = MACIO_IN32(offset);
0164     return 0;
0165 }
0166
0167 static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask)
0168 {
0169     struct macio_chip *macio = func->driver_data;
0170     unsigned long flags;
0171
0172     raw_spin_lock_irqsave(&feature_lock, flags);
0173     MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) | (value & mask));
0174     raw_spin_unlock_irqrestore(&feature_lock, flags);
0175     return 0;
0176 }
0177
0178 static int macio_do_read_reg8(PMF_STD_ARGS, u32 offset)
0179 {
0180     struct macio_chip *macio = func->driver_data;
0181
0182     /* Check if we have room for reply */
0183     if (args == NULL || args->count == 0 || args->u[0].p == NULL)
0184         return -EINVAL;
0185
0186     *((u8 *)(args->u[0].p)) = MACIO_IN8(offset);
0187     return 0;
0188 }
0189
0190 static int macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
0191                     u32 shift, u32 xor)
0192 {
0193     struct macio_chip *macio = func->driver_data;
0194
0195     /* Check if we have room for reply */
0196     if (args == NULL || args->count == 0 || args->u[0].p == NULL)
0197         return -EINVAL;
0198
0199     *args->u[0].p = ((MACIO_IN32(offset) & mask) >> shift) ^ xor;
0200     return 0;
0201 }
0202
0203 static int macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
0204                    u32 shift, u32 xor)
0205 {
0206     struct macio_chip *macio = func->driver_data;
0207
0208     /* Check if we have room for reply */
0209     if (args == NULL || args->count == 0 || args->u[0].p == NULL)
0210         return -EINVAL;
0211
0212     *((u8 *)(args->u[0].p)) = ((MACIO_IN8(offset) & mask) >> shift) ^ xor;
0213     return 0;
0214 }
0215
0216 static int macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift,
0217                     u32 mask)
0218 {
0219     struct macio_chip *macio = func->driver_data;
0220     unsigned long flags;
0221     u32 tmp, val;
0222
0223     /* Check args */
0224     if (args == NULL || args->count == 0)
0225         return -EINVAL;
0226
0227     raw_spin_lock_irqsave(&feature_lock, flags);
0228     tmp = MACIO_IN32(offset);
0229     val = args->u[0].v << shift;
0230     tmp = (tmp & ~mask) | (val & mask);
0231     MACIO_OUT32(offset, tmp);
0232     raw_spin_unlock_irqrestore(&feature_lock, flags);
0233     return 0;
0234 }
0235
0236 static int macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift,
0237                    u32 mask)
0238 {
0239     struct macio_chip *macio = func->driver_data;
0240     unsigned long flags;
0241     u32 tmp, val;
0242
0243     /* Check args */
0244     if (args == NULL || args->count == 0)
0245         return -EINVAL;
0246
0247     raw_spin_lock_irqsave(&feature_lock, flags);
0248     tmp = MACIO_IN8(offset);
0249     val = args->u[0].v << shift;
0250     tmp = (tmp & ~mask) | (val & mask);
0251     MACIO_OUT8(offset, tmp);
0252     raw_spin_unlock_irqrestore(&feature_lock, flags);
0253     return 0;
0254 }
0255
0256 static struct pmf_handlers macio_mmio_handlers = {
0257     .write_reg32        = macio_do_write_reg32,
0258     .read_reg32     = macio_do_read_reg32,
0259     .write_reg8     = macio_do_write_reg8,
0260     .read_reg8      = macio_do_read_reg8,
0261     .read_reg32_msrx    = macio_do_read_reg32_msrx,
0262     .read_reg8_msrx     = macio_do_read_reg8_msrx,
0263     .write_reg32_slm    = macio_do_write_reg32_slm,
0264     .write_reg8_slm     = macio_do_write_reg8_slm,
0265     .delay          = macio_do_delay,
0266 };
0267
0268 static void __init macio_mmio_init_one(struct macio_chip *macio)
0269 {
0270     DBG("Installing MMIO functions for macio %pOF\n",
0271         macio->of_node);
0272
0273     pmf_register_driver(macio->of_node, &macio_mmio_handlers, macio);
0274 }
0275
0276 static struct device_node *unin_hwclock;
0277
0278 static int unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
0279 {
0280     unsigned long flags;
0281
0282     raw_spin_lock_irqsave(&feature_lock, flags);
0283     /* This is fairly bogus in darwin, but it should work for our needs
0284      * implemeted that way:
0285      */
0286     UN_OUT(offset, (UN_IN(offset) & ~mask) | (value & mask));
0287     raw_spin_unlock_irqrestore(&feature_lock, flags);
0288     return 0;
0289 }
0290
0291
0292 static struct pmf_handlers unin_mmio_handlers = {
0293     .write_reg32        = unin_do_write_reg32,
0294     .delay          = macio_do_delay,
0295 };
0296
0297 static void __init uninorth_install_pfunc(void)
0298 {
0299     struct device_node *np;
0300
0301     DBG("Installing functions for UniN %pOF\n",
0302         uninorth_node);
0303
0304     /*
0305      * Install handlers for the bridge itself
0306      */
0307     pmf_register_driver(uninorth_node, &unin_mmio_handlers, NULL);
0308     pmf_do_functions(uninorth_node, NULL, 0, PMF_FLAGS_ON_INIT, NULL);
0309
0310
0311     /*
0312      * Install handlers for the hwclock child if any
0313      */
0314     for (np = NULL; (np = of_get_next_child(uninorth_node, np)) != NULL;)
0315         if (of_node_name_eq(np, "hw-clock")) {
0316             unin_hwclock = np;
0317             break;
0318         }
0319     if (unin_hwclock) {
0320         DBG("Installing functions for UniN clock %pOF\n",
0321             unin_hwclock);
0322         pmf_register_driver(unin_hwclock, &unin_mmio_handlers, NULL);
0323         pmf_do_functions(unin_hwclock, NULL, 0, PMF_FLAGS_ON_INIT,
0324                  NULL);
0325     }
0326 }
0327
0328 /* We export this as the SMP code might init us early */
0329 int __init pmac_pfunc_base_install(void)
0330 {
0331     static int pfbase_inited;
0332     int i;
0333
0334     if (pfbase_inited)
0335         return 0;
0336     pfbase_inited = 1;
0337
0338     if (!machine_is(powermac))
0339         return 0;
0340
0341     DBG("Installing base platform functions...\n");
0342
0343     /*
0344      * Locate mac-io chips and install handlers
0345      */
0346     for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
0347         if (macio_chips[i].of_node) {
0348             macio_mmio_init_one(&macio_chips[i]);
0349             macio_gpio_init_one(&macio_chips[i]);
0350         }
0351     }
0352
0353     /*
0354      * Install handlers for northbridge and direct mapped hwclock
0355      * if any. We do not implement the config space access callback
0356      * which is only ever used for functions that we do not call in
0357      * the current driver (enabling/disabling cells in U2, mostly used
0358      * to restore the PCI settings, we do that differently)
0359      */
0360     if (uninorth_node && uninorth_base)
0361         uninorth_install_pfunc();
0362
0363     DBG("All base functions installed\n");
0364
0365     return 0;
0366 }
0367 machine_arch_initcall(powermac, pmac_pfunc_base_install);
0368
0369 #ifdef CONFIG_PM
0370
0371 /* Those can be called by pmac_feature. Ultimately, I should use a sysdev
0372  * or a device, but for now, that's good enough until I sort out some
0373  * ordering issues. Also, we do not bother with GPIOs, as so far I yet have
0374  * to see a case where a GPIO function has the on-suspend or on-resume bit
0375  */
0376 void pmac_pfunc_base_suspend(void)
0377 {
0378     int i;
0379
0380     for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
0381         if (macio_chips[i].of_node)
0382             pmf_do_functions(macio_chips[i].of_node, NULL, 0,
0383                      PMF_FLAGS_ON_SLEEP, NULL);
0384     }
0385     if (uninorth_node)
0386         pmf_do_functions(uninorth_node, NULL, 0,
0387                  PMF_FLAGS_ON_SLEEP, NULL);
0388     if (unin_hwclock)
0389         pmf_do_functions(unin_hwclock, NULL, 0,
0390                  PMF_FLAGS_ON_SLEEP, NULL);
0391 }
0392
0393 void pmac_pfunc_base_resume(void)
0394 {
0395     int i;
0396
0397     if (unin_hwclock)
0398         pmf_do_functions(unin_hwclock, NULL, 0,
0399                  PMF_FLAGS_ON_WAKE, NULL);
0400     if (uninorth_node)
0401         pmf_do_functions(uninorth_node, NULL, 0,
0402                  PMF_FLAGS_ON_WAKE, NULL);
0403     for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
0404         if (macio_chips[i].of_node)
0405             pmf_do_functions(macio_chips[i].of_node, NULL, 0,
0406                      PMF_FLAGS_ON_WAKE, NULL);
0407     }
0408 }
0409
0410 #endif /* CONFIG_PM */