platforms/pasemi/msi.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright 2007, Olof Johansson, PA Semi
0004  *
0005  * Based on arch/powerpc/sysdev/mpic_u3msi.c:
0006  *
0007  * Copyright 2006, Segher Boessenkool, IBM Corporation.
0008  * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
0009  */
0010
0011 #include <linux/irq.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/msi.h>
0014 #include <asm/mpic.h>
0015 #include <asm/hw_irq.h>
0016 #include <asm/ppc-pci.h>
0017 #include <asm/msi_bitmap.h>
0018
0019 #include <sysdev/mpic.h>
0020
0021 /* Allocate 16 interrupts per device, to give an alignment of 16,
0022  * since that's the size of the grouping w.r.t. affinity. If someone
0023  * needs more than 32 MSI's down the road we'll have to rethink this,
0024  * but it should be OK for now.
0025  */
0026 #define ALLOC_CHUNK 16
0027
0028 #define PASEMI_MSI_ADDR 0xfc080000
0029
0030 /* A bit ugly, can we get this from the pci_dev somehow? */
0031 static struct mpic *msi_mpic;
0032
0033
0034 static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
0035 {
0036     pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
0037     pci_msi_mask_irq(data);
0038     mpic_mask_irq(data);
0039 }
0040
0041 static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
0042 {
0043     pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
0044     mpic_unmask_irq(data);
0045     pci_msi_unmask_irq(data);
0046 }
0047
0048 static struct irq_chip mpic_pasemi_msi_chip = {
0049     .irq_shutdown       = mpic_pasemi_msi_mask_irq,
0050     .irq_mask       = mpic_pasemi_msi_mask_irq,
0051     .irq_unmask     = mpic_pasemi_msi_unmask_irq,
0052     .irq_eoi        = mpic_end_irq,
0053     .irq_set_type       = mpic_set_irq_type,
0054     .irq_set_affinity   = mpic_set_affinity,
0055     .name           = "PASEMI-MSI",
0056 };
0057
0058 static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
0059 {
0060     struct msi_desc *entry;
0061     irq_hw_number_t hwirq;
0062
0063     pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
0064
0065     msi_for_each_desc(entry, &pdev->dev, MSI_DESC_ASSOCIATED) {
0066         hwirq = virq_to_hw(entry->irq);
0067         irq_set_msi_desc(entry->irq, NULL);
0068         irq_dispose_mapping(entry->irq);
0069         msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, ALLOC_CHUNK);
0070     }
0071 }
0072
0073 static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
0074 {
0075     unsigned int virq;
0076     struct msi_desc *entry;
0077     struct msi_msg msg;
0078     int hwirq;
0079
0080     if (type == PCI_CAP_ID_MSIX)
0081         pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
0082     pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
0083          pdev, nvec, type);
0084
0085     msg.address_hi = 0;
0086     msg.address_lo = PASEMI_MSI_ADDR;
0087
0088     msi_for_each_desc(entry, &pdev->dev, MSI_DESC_NOTASSOCIATED) {
0089         /* Allocate 16 interrupts for now, since that's the grouping for
0090          * affinity. This can be changed later if it turns out 32 is too
0091          * few MSIs for someone, but restrictions will apply to how the
0092          * sources can be changed independently.
0093          */
0094         hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap,
0095                         ALLOC_CHUNK);
0096         if (hwirq < 0) {
0097             pr_debug("pasemi_msi: failed allocating hwirq\n");
0098             return hwirq;
0099         }
0100
0101         virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
0102         if (!virq) {
0103             pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n",
0104                   hwirq);
0105             msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq,
0106                            ALLOC_CHUNK);
0107             return -ENOSPC;
0108         }
0109
0110         /* Vector on MSI is really an offset, the hardware adds
0111          * it to the value written at the magic address. So set
0112          * it to 0 to remain sane.
0113          */
0114         mpic_set_vector(virq, 0);
0115
0116         irq_set_msi_desc(virq, entry);
0117         irq_set_chip(virq, &mpic_pasemi_msi_chip);
0118         irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
0119
0120         pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
0121              "addr 0x%x\n", virq, hwirq, msg.address_lo);
0122
0123         /* Likewise, the device writes [0...511] into the target
0124          * register to generate MSI [512...1023]
0125          */
0126         msg.data = hwirq-0x200;
0127         pci_write_msi_msg(virq, &msg);
0128     }
0129
0130     return 0;
0131 }
0132
0133 int __init mpic_pasemi_msi_init(struct mpic *mpic)
0134 {
0135     int rc;
0136     struct pci_controller *phb;
0137     struct device_node *of_node;
0138
0139     of_node = irq_domain_get_of_node(mpic->irqhost);
0140     if (!of_node ||
0141         !of_device_is_compatible(of_node,
0142                      "pasemi,pwrficient-openpic"))
0143         return -ENODEV;
0144
0145     rc = mpic_msi_init_allocator(mpic);
0146     if (rc) {
0147         pr_debug("pasemi_msi: Error allocating bitmap!\n");
0148         return rc;
0149     }
0150
0151     pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
0152
0153     msi_mpic = mpic;
0154     list_for_each_entry(phb, &hose_list, list_node) {
0155         WARN_ON(phb->controller_ops.setup_msi_irqs);
0156         phb->controller_ops.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
0157         phb->controller_ops.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
0158     }
0159
0160     return 0;
0161 }