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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
0004  *            IBM Corp.
0005  */
0006 
0007 #undef DEBUG
0008 
0009 #include <linux/kernel.h>
0010 #include <linux/pci.h>
0011 #include <linux/delay.h>
0012 #include <linux/string.h>
0013 #include <linux/init.h>
0014 #include <linux/irq.h>
0015 #include <linux/of_irq.h>
0016 
0017 #include <asm/sections.h>
0018 #include <asm/io.h>
0019 #include <asm/pci-bridge.h>
0020 #include <asm/machdep.h>
0021 #include <asm/iommu.h>
0022 #include <asm/ppc-pci.h>
0023 #include <asm/isa-bridge.h>
0024 
0025 #include "maple.h"
0026 
0027 #ifdef DEBUG
0028 #define DBG(x...) printk(x)
0029 #else
0030 #define DBG(x...)
0031 #endif
0032 
0033 static struct pci_controller *u3_agp, *u3_ht, *u4_pcie;
0034 
0035 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
0036 {
0037     for (; node; node = node->sibling) {
0038         const int *bus_range;
0039         const unsigned int *class_code;
0040         int len;
0041 
0042         /* For PCI<->PCI bridges or CardBus bridges, we go down */
0043         class_code = of_get_property(node, "class-code", NULL);
0044         if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
0045             (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
0046             continue;
0047         bus_range = of_get_property(node, "bus-range", &len);
0048         if (bus_range != NULL && len > 2 * sizeof(int)) {
0049             if (bus_range[1] > higher)
0050                 higher = bus_range[1];
0051         }
0052         higher = fixup_one_level_bus_range(node->child, higher);
0053     }
0054     return higher;
0055 }
0056 
0057 /* This routine fixes the "bus-range" property of all bridges in the
0058  * system since they tend to have their "last" member wrong on macs
0059  *
0060  * Note that the bus numbers manipulated here are OF bus numbers, they
0061  * are not Linux bus numbers.
0062  */
0063 static void __init fixup_bus_range(struct device_node *bridge)
0064 {
0065     int *bus_range;
0066     struct property *prop;
0067     int len;
0068 
0069     /* Lookup the "bus-range" property for the hose */
0070     prop = of_find_property(bridge, "bus-range", &len);
0071     if (prop == NULL  || prop->value == NULL || len < 2 * sizeof(int)) {
0072         printk(KERN_WARNING "Can't get bus-range for %pOF\n",
0073                    bridge);
0074         return;
0075     }
0076     bus_range = prop->value;
0077     bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
0078 }
0079 
0080 
0081 static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
0082 {
0083     return (1 << (unsigned long)PCI_SLOT(devfn)) |
0084         ((unsigned long)PCI_FUNC(devfn) << 8) |
0085         ((unsigned long)off & 0xFCUL);
0086 }
0087 
0088 static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
0089 {
0090     return ((unsigned long)bus << 16) |
0091         ((unsigned long)devfn << 8) |
0092         ((unsigned long)off & 0xFCUL) |
0093         1UL;
0094 }
0095 
0096 static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
0097                        u8 bus, u8 dev_fn, u8 offset)
0098 {
0099     unsigned int caddr;
0100 
0101     if (bus == hose->first_busno) {
0102         if (dev_fn < (11 << 3))
0103             return NULL;
0104         caddr = u3_agp_cfa0(dev_fn, offset);
0105     } else
0106         caddr = u3_agp_cfa1(bus, dev_fn, offset);
0107 
0108     /* Uninorth will return garbage if we don't read back the value ! */
0109     do {
0110         out_le32(hose->cfg_addr, caddr);
0111     } while (in_le32(hose->cfg_addr) != caddr);
0112 
0113     offset &= 0x07;
0114     return hose->cfg_data + offset;
0115 }
0116 
0117 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
0118                   int offset, int len, u32 *val)
0119 {
0120     struct pci_controller *hose;
0121     volatile void __iomem *addr;
0122 
0123     hose = pci_bus_to_host(bus);
0124     if (hose == NULL)
0125         return PCIBIOS_DEVICE_NOT_FOUND;
0126 
0127     addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
0128     if (!addr)
0129         return PCIBIOS_DEVICE_NOT_FOUND;
0130     /*
0131      * Note: the caller has already checked that offset is
0132      * suitably aligned and that len is 1, 2 or 4.
0133      */
0134     switch (len) {
0135     case 1:
0136         *val = in_8(addr);
0137         break;
0138     case 2:
0139         *val = in_le16(addr);
0140         break;
0141     default:
0142         *val = in_le32(addr);
0143         break;
0144     }
0145     return PCIBIOS_SUCCESSFUL;
0146 }
0147 
0148 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
0149                    int offset, int len, u32 val)
0150 {
0151     struct pci_controller *hose;
0152     volatile void __iomem *addr;
0153 
0154     hose = pci_bus_to_host(bus);
0155     if (hose == NULL)
0156         return PCIBIOS_DEVICE_NOT_FOUND;
0157 
0158     addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
0159     if (!addr)
0160         return PCIBIOS_DEVICE_NOT_FOUND;
0161     /*
0162      * Note: the caller has already checked that offset is
0163      * suitably aligned and that len is 1, 2 or 4.
0164      */
0165     switch (len) {
0166     case 1:
0167         out_8(addr, val);
0168         break;
0169     case 2:
0170         out_le16(addr, val);
0171         break;
0172     default:
0173         out_le32(addr, val);
0174         break;
0175     }
0176     return PCIBIOS_SUCCESSFUL;
0177 }
0178 
0179 static struct pci_ops u3_agp_pci_ops =
0180 {
0181     .read = u3_agp_read_config,
0182     .write = u3_agp_write_config,
0183 };
0184 
0185 static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
0186 {
0187     return (devfn << 8) | off;
0188 }
0189 
0190 static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
0191 {
0192     return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
0193 }
0194 
0195 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
0196                       u8 bus, u8 devfn, u8 offset)
0197 {
0198     if (bus == hose->first_busno) {
0199         if (PCI_SLOT(devfn) == 0)
0200             return NULL;
0201         return hose->cfg_data + u3_ht_cfa0(devfn, offset);
0202     } else
0203         return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
0204 }
0205 
0206 static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,
0207                   int len, u32 *val)
0208 {
0209     volatile void __iomem *addr;
0210 
0211     addr = hose->cfg_addr;
0212     addr += ((offset & ~3) << 2) + (4 - len - (offset & 3));
0213 
0214     switch (len) {
0215     case 1:
0216         *val = in_8(addr);
0217         break;
0218     case 2:
0219         *val = in_be16(addr);
0220         break;
0221     default:
0222         *val = in_be32(addr);
0223         break;
0224     }
0225 
0226     return PCIBIOS_SUCCESSFUL;
0227 }
0228 
0229 static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
0230                   int len, u32 val)
0231 {
0232     volatile void __iomem *addr;
0233 
0234     addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));
0235 
0236     if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)
0237         return PCIBIOS_SUCCESSFUL;
0238 
0239     switch (len) {
0240     case 1:
0241         out_8(addr, val);
0242         break;
0243     case 2:
0244         out_be16(addr, val);
0245         break;
0246     default:
0247         out_be32(addr, val);
0248         break;
0249     }
0250 
0251     return PCIBIOS_SUCCESSFUL;
0252 }
0253 
0254 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
0255                  int offset, int len, u32 *val)
0256 {
0257     struct pci_controller *hose;
0258     volatile void __iomem *addr;
0259 
0260     hose = pci_bus_to_host(bus);
0261     if (hose == NULL)
0262         return PCIBIOS_DEVICE_NOT_FOUND;
0263 
0264     if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
0265         return u3_ht_root_read_config(hose, offset, len, val);
0266 
0267     if (offset > 0xff)
0268         return PCIBIOS_BAD_REGISTER_NUMBER;
0269 
0270     addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
0271     if (!addr)
0272         return PCIBIOS_DEVICE_NOT_FOUND;
0273 
0274     /*
0275      * Note: the caller has already checked that offset is
0276      * suitably aligned and that len is 1, 2 or 4.
0277      */
0278     switch (len) {
0279     case 1:
0280         *val = in_8(addr);
0281         break;
0282     case 2:
0283         *val = in_le16(addr);
0284         break;
0285     default:
0286         *val = in_le32(addr);
0287         break;
0288     }
0289     return PCIBIOS_SUCCESSFUL;
0290 }
0291 
0292 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
0293                   int offset, int len, u32 val)
0294 {
0295     struct pci_controller *hose;
0296     volatile void __iomem *addr;
0297 
0298     hose = pci_bus_to_host(bus);
0299     if (hose == NULL)
0300         return PCIBIOS_DEVICE_NOT_FOUND;
0301 
0302     if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
0303         return u3_ht_root_write_config(hose, offset, len, val);
0304 
0305     if (offset > 0xff)
0306         return PCIBIOS_BAD_REGISTER_NUMBER;
0307 
0308     addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
0309     if (!addr)
0310         return PCIBIOS_DEVICE_NOT_FOUND;
0311     /*
0312      * Note: the caller has already checked that offset is
0313      * suitably aligned and that len is 1, 2 or 4.
0314      */
0315     switch (len) {
0316     case 1:
0317         out_8(addr, val);
0318         break;
0319     case 2:
0320         out_le16(addr, val);
0321         break;
0322     default:
0323         out_le32(addr, val);
0324         break;
0325     }
0326     return PCIBIOS_SUCCESSFUL;
0327 }
0328 
0329 static struct pci_ops u3_ht_pci_ops =
0330 {
0331     .read = u3_ht_read_config,
0332     .write = u3_ht_write_config,
0333 };
0334 
0335 static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off)
0336 {
0337     return (1 << PCI_SLOT(devfn))   |
0338            (PCI_FUNC(devfn) << 8)   |
0339            ((off >> 8) << 28)   |
0340            (off & 0xfcu);
0341 }
0342 
0343 static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn,
0344                  unsigned int off)
0345 {
0346         return (bus << 16)      |
0347            (devfn << 8)     |
0348            ((off >> 8) << 28)   |
0349            (off & 0xfcu)        | 1u;
0350 }
0351 
0352 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
0353                                         u8 bus, u8 dev_fn, int offset)
0354 {
0355         unsigned int caddr;
0356 
0357         if (bus == hose->first_busno)
0358                 caddr = u4_pcie_cfa0(dev_fn, offset);
0359         else
0360                 caddr = u4_pcie_cfa1(bus, dev_fn, offset);
0361 
0362         /* Uninorth will return garbage if we don't read back the value ! */
0363         do {
0364                 out_le32(hose->cfg_addr, caddr);
0365         } while (in_le32(hose->cfg_addr) != caddr);
0366 
0367         offset &= 0x03;
0368         return hose->cfg_data + offset;
0369 }
0370 
0371 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
0372                                int offset, int len, u32 *val)
0373 {
0374         struct pci_controller *hose;
0375         volatile void __iomem *addr;
0376 
0377         hose = pci_bus_to_host(bus);
0378         if (hose == NULL)
0379                 return PCIBIOS_DEVICE_NOT_FOUND;
0380         if (offset >= 0x1000)
0381                 return  PCIBIOS_BAD_REGISTER_NUMBER;
0382         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
0383         if (!addr)
0384                 return PCIBIOS_DEVICE_NOT_FOUND;
0385         /*
0386          * Note: the caller has already checked that offset is
0387          * suitably aligned and that len is 1, 2 or 4.
0388          */
0389         switch (len) {
0390         case 1:
0391                 *val = in_8(addr);
0392                 break;
0393         case 2:
0394                 *val = in_le16(addr);
0395                 break;
0396         default:
0397                 *val = in_le32(addr);
0398                 break;
0399         }
0400         return PCIBIOS_SUCCESSFUL;
0401 }
0402 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
0403                                 int offset, int len, u32 val)
0404 {
0405         struct pci_controller *hose;
0406         volatile void __iomem *addr;
0407 
0408         hose = pci_bus_to_host(bus);
0409         if (hose == NULL)
0410                 return PCIBIOS_DEVICE_NOT_FOUND;
0411         if (offset >= 0x1000)
0412                 return  PCIBIOS_BAD_REGISTER_NUMBER;
0413         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
0414         if (!addr)
0415                 return PCIBIOS_DEVICE_NOT_FOUND;
0416         /*
0417          * Note: the caller has already checked that offset is
0418          * suitably aligned and that len is 1, 2 or 4.
0419          */
0420         switch (len) {
0421         case 1:
0422                 out_8(addr, val);
0423                 break;
0424         case 2:
0425                 out_le16(addr, val);
0426                 break;
0427         default:
0428                 out_le32(addr, val);
0429                 break;
0430         }
0431         return PCIBIOS_SUCCESSFUL;
0432 }
0433 
0434 static struct pci_ops u4_pcie_pci_ops =
0435 {
0436     .read = u4_pcie_read_config,
0437     .write = u4_pcie_write_config,
0438 };
0439 
0440 static void __init setup_u3_agp(struct pci_controller* hose)
0441 {
0442     /* On G5, we move AGP up to high bus number so we don't need
0443      * to reassign bus numbers for HT. If we ever have P2P bridges
0444      * on AGP, we'll have to move pci_assign_all_buses to the
0445      * pci_controller structure so we enable it for AGP and not for
0446      * HT childs.
0447      * We hard code the address because of the different size of
0448      * the reg address cell, we shall fix that by killing struct
0449      * reg_property and using some accessor functions instead
0450      */
0451     hose->first_busno = 0xf0;
0452     hose->last_busno = 0xff;
0453     hose->ops = &u3_agp_pci_ops;
0454     hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
0455     hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
0456 
0457     u3_agp = hose;
0458 }
0459 
0460 static void __init setup_u4_pcie(struct pci_controller* hose)
0461 {
0462         /* We currently only implement the "non-atomic" config space, to
0463          * be optimised later.
0464          */
0465         hose->ops = &u4_pcie_pci_ops;
0466         hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
0467         hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
0468 
0469         u4_pcie = hose;
0470 }
0471 
0472 static void __init setup_u3_ht(struct pci_controller* hose)
0473 {
0474     hose->ops = &u3_ht_pci_ops;
0475 
0476     /* We hard code the address because of the different size of
0477      * the reg address cell, we shall fix that by killing struct
0478      * reg_property and using some accessor functions instead
0479      */
0480     hose->cfg_data = ioremap(0xf2000000, 0x02000000);
0481     hose->cfg_addr = ioremap(0xf8070000, 0x1000);
0482 
0483     hose->first_busno = 0;
0484     hose->last_busno = 0xef;
0485 
0486     u3_ht = hose;
0487 }
0488 
0489 static int __init maple_add_bridge(struct device_node *dev)
0490 {
0491     int len;
0492     struct pci_controller *hose;
0493     char* disp_name;
0494     const int *bus_range;
0495     int primary = 1;
0496 
0497     DBG("Adding PCI host bridge %pOF\n", dev);
0498 
0499     bus_range = of_get_property(dev, "bus-range", &len);
0500     if (bus_range == NULL || len < 2 * sizeof(int)) {
0501         printk(KERN_WARNING "Can't get bus-range for %pOF, assume bus 0\n",
0502         dev);
0503     }
0504 
0505     hose = pcibios_alloc_controller(dev);
0506     if (hose == NULL)
0507         return -ENOMEM;
0508     hose->first_busno = bus_range ? bus_range[0] : 0;
0509     hose->last_busno = bus_range ? bus_range[1] : 0xff;
0510     hose->controller_ops = maple_pci_controller_ops;
0511 
0512     disp_name = NULL;
0513     if (of_device_is_compatible(dev, "u3-agp")) {
0514         setup_u3_agp(hose);
0515         disp_name = "U3-AGP";
0516         primary = 0;
0517     } else if (of_device_is_compatible(dev, "u3-ht")) {
0518         setup_u3_ht(hose);
0519         disp_name = "U3-HT";
0520         primary = 1;
0521         } else if (of_device_is_compatible(dev, "u4-pcie")) {
0522                 setup_u4_pcie(hose);
0523                 disp_name = "U4-PCIE";
0524                 primary = 0;
0525     }
0526     printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
0527         disp_name, hose->first_busno, hose->last_busno);
0528 
0529     /* Interpret the "ranges" property */
0530     /* This also maps the I/O region and sets isa_io/mem_base */
0531     pci_process_bridge_OF_ranges(hose, dev, primary);
0532 
0533     /* Fixup "bus-range" OF property */
0534     fixup_bus_range(dev);
0535 
0536     /* Check for legacy IOs */
0537     isa_bridge_find_early(hose);
0538 
0539     /* create pci_dn's for DT nodes under this PHB */
0540     pci_devs_phb_init_dynamic(hose);
0541 
0542     return 0;
0543 }
0544 
0545 
0546 void maple_pci_irq_fixup(struct pci_dev *dev)
0547 {
0548     DBG(" -> maple_pci_irq_fixup\n");
0549 
0550     /* Fixup IRQ for PCIe host */
0551     if (u4_pcie != NULL && dev->bus->number == 0 &&
0552         pci_bus_to_host(dev->bus) == u4_pcie) {
0553         printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
0554         dev->irq = irq_create_mapping(NULL, 1);
0555         if (dev->irq)
0556             irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
0557     }
0558 
0559     /* Hide AMD8111 IDE interrupt when in legacy mode so
0560      * the driver calls pci_get_legacy_ide_irq()
0561      */
0562     if (dev->vendor == PCI_VENDOR_ID_AMD &&
0563         dev->device == PCI_DEVICE_ID_AMD_8111_IDE &&
0564         (dev->class & 5) != 5) {
0565         dev->irq = 0;
0566     }
0567 
0568     DBG(" <- maple_pci_irq_fixup\n");
0569 }
0570 
0571 static int maple_pci_root_bridge_prepare(struct pci_host_bridge *bridge)
0572 {
0573     struct pci_controller *hose = pci_bus_to_host(bridge->bus);
0574     struct device_node *np, *child;
0575 
0576     if (hose != u3_agp)
0577         return 0;
0578 
0579     /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
0580      * assume there is no P2P bridge on the AGP bus, which should be a
0581      * safe assumptions hopefully.
0582      */
0583     np = hose->dn;
0584     PCI_DN(np)->busno = 0xf0;
0585     for_each_child_of_node(np, child)
0586         PCI_DN(child)->busno = 0xf0;
0587 
0588     return 0;
0589 }
0590 
0591 void __init maple_pci_init(void)
0592 {
0593     struct device_node *np, *root;
0594     struct device_node *ht = NULL;
0595 
0596     /* Probe root PCI hosts, that is on U3 the AGP host and the
0597      * HyperTransport host. That one is actually "kept" around
0598      * and actually added last as it's resource management relies
0599      * on the AGP resources to have been setup first
0600      */
0601     root = of_find_node_by_path("/");
0602     if (root == NULL) {
0603         printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
0604         return;
0605     }
0606     for_each_child_of_node(root, np) {
0607         if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "ht"))
0608             continue;
0609         if ((of_device_is_compatible(np, "u4-pcie") ||
0610              of_device_is_compatible(np, "u3-agp")) &&
0611             maple_add_bridge(np) == 0)
0612             of_node_get(np);
0613 
0614         if (of_device_is_compatible(np, "u3-ht")) {
0615             of_node_get(np);
0616             ht = np;
0617         }
0618     }
0619     of_node_put(root);
0620 
0621     /* Now setup the HyperTransport host if we found any
0622      */
0623     if (ht && maple_add_bridge(ht) != 0)
0624         of_node_put(ht);
0625 
0626     ppc_md.pcibios_root_bridge_prepare = maple_pci_root_bridge_prepare;
0627 
0628     /* Tell pci.c to not change any resource allocations.  */
0629     pci_add_flags(PCI_PROBE_ONLY);
0630 }
0631 
0632 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
0633 {
0634     struct device_node *np;
0635     unsigned int defirq = channel ? 15 : 14;
0636     unsigned int irq;
0637 
0638     if (pdev->vendor != PCI_VENDOR_ID_AMD ||
0639         pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
0640         return defirq;
0641 
0642     np = pci_device_to_OF_node(pdev);
0643     if (np == NULL) {
0644         printk("Failed to locate OF node for IDE %s\n",
0645                pci_name(pdev));
0646         return defirq;
0647     }
0648     irq = irq_of_parse_and_map(np, channel & 0x1);
0649     if (!irq) {
0650         printk("Failed to map onboard IDE interrupt for channel %d\n",
0651                channel);
0652         return defirq;
0653     }
0654     return irq;
0655 }
0656 
0657 static void quirk_ipr_msi(struct pci_dev *dev)
0658 {
0659     /* Something prevents MSIs from the IPR from working on Bimini,
0660      * and the driver has no smarts to recover. So disable MSI
0661      * on it for now. */
0662 
0663     if (machine_is(maple)) {
0664         dev->no_msi = 1;
0665         dev_info(&dev->dev, "Quirk disabled MSI\n");
0666     }
0667 }
0668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
0669             quirk_ipr_msi);
0670 
0671 struct pci_controller_ops maple_pci_controller_ops = {
0672 };
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