powerpc/platforms/fsl_uli1575.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * ULI M1575 setup code - specific to Freescale boards
0004  *
0005  * Copyright 2007 Freescale Semiconductor Inc.
0006  */
0007
0008 #include <linux/stddef.h>
0009 #include <linux/kernel.h>
0010 #include <linux/pci.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/mc146818rtc.h>
0013 #include <linux/of_irq.h>
0014
0015 #include <asm/pci-bridge.h>
0016
0017 #define ULI_PIRQA   0x08
0018 #define ULI_PIRQB   0x09
0019 #define ULI_PIRQC   0x0a
0020 #define ULI_PIRQD   0x0b
0021 #define ULI_PIRQE   0x0c
0022 #define ULI_PIRQF   0x0d
0023 #define ULI_PIRQG   0x0e
0024
0025 #define ULI_8259_NONE   0x00
0026 #define ULI_8259_IRQ1   0x08
0027 #define ULI_8259_IRQ3   0x02
0028 #define ULI_8259_IRQ4   0x04
0029 #define ULI_8259_IRQ5   0x05
0030 #define ULI_8259_IRQ6   0x07
0031 #define ULI_8259_IRQ7   0x06
0032 #define ULI_8259_IRQ9   0x01
0033 #define ULI_8259_IRQ10  0x03
0034 #define ULI_8259_IRQ11  0x09
0035 #define ULI_8259_IRQ12  0x0b
0036 #define ULI_8259_IRQ14  0x0d
0037 #define ULI_8259_IRQ15  0x0f
0038
0039 u8 uli_pirq_to_irq[8] = {
0040     ULI_8259_IRQ9,      /* PIRQA */
0041     ULI_8259_IRQ10,     /* PIRQB */
0042     ULI_8259_IRQ11,     /* PIRQC */
0043     ULI_8259_IRQ12,     /* PIRQD */
0044     ULI_8259_IRQ5,      /* PIRQE */
0045     ULI_8259_IRQ6,      /* PIRQF */
0046     ULI_8259_IRQ7,      /* PIRQG */
0047     ULI_8259_NONE,      /* PIRQH */
0048 };
0049
0050 static inline bool is_quirk_valid(void)
0051 {
0052     return (machine_is(mpc86xx_hpcn) ||
0053         machine_is(mpc8544_ds) ||
0054         machine_is(p2020_ds) ||
0055         machine_is(mpc8572_ds));
0056 }
0057
0058 /* Bridge */
0059 static void early_uli5249(struct pci_dev *dev)
0060 {
0061     unsigned char temp;
0062
0063     if (!is_quirk_valid())
0064         return;
0065
0066     pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO |
0067          PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
0068
0069     /* read/write lock */
0070     pci_read_config_byte(dev, 0x7c, &temp);
0071     pci_write_config_byte(dev, 0x7c, 0x80);
0072
0073     /* set as P2P bridge */
0074     pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
0075     dev->class |= 0x1;
0076
0077     /* restore lock */
0078     pci_write_config_byte(dev, 0x7c, temp);
0079 }
0080
0081
0082 static void quirk_uli1575(struct pci_dev *dev)
0083 {
0084     int i;
0085
0086     if (!is_quirk_valid())
0087         return;
0088
0089     /*
0090      * ULI1575 interrupts route setup
0091      */
0092
0093     /* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */
0094     for (i = 0; i < 4; i++) {
0095         u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4);
0096         pci_write_config_byte(dev, 0x48 + i, val);
0097     }
0098
0099     /* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */
0100     pci_write_config_byte(dev, 0x86, ULI_PIRQD);
0101
0102     /* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */
0103     pci_write_config_byte(dev, 0x87, ULI_PIRQA);
0104
0105     /* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */
0106     pci_write_config_byte(dev, 0x88, ULI_PIRQB);
0107
0108     /* Lan controller: dev 27, func 0 - IRQ6 */
0109     pci_write_config_byte(dev, 0x89, ULI_PIRQF);
0110
0111     /* AC97 Audio controller: dev 29, func 0 - IRQ6 */
0112     pci_write_config_byte(dev, 0x8a, ULI_PIRQF);
0113
0114     /* Modem controller: dev 29, func 1 - IRQ6 */
0115     pci_write_config_byte(dev, 0x8b, ULI_PIRQF);
0116
0117     /* HD Audio controller: dev 29, func 2 - IRQ6 */
0118     pci_write_config_byte(dev, 0x8c, ULI_PIRQF);
0119
0120     /* SATA controller: dev 31, func 1 - IRQ5 */
0121     pci_write_config_byte(dev, 0x8d, ULI_PIRQE);
0122
0123     /* SMB interrupt: dev 30, func 1 - IRQ7 */
0124     pci_write_config_byte(dev, 0x8e, ULI_PIRQG);
0125
0126     /* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */
0127     pci_write_config_byte(dev, 0x8f, ULI_PIRQG);
0128
0129     /* USB 2.0 controller: dev 28, func 3 */
0130     pci_write_config_byte(dev, 0x74, ULI_8259_IRQ11);
0131
0132     /* Primary PATA IDE IRQ: 14
0133      * Secondary PATA IDE IRQ: 15
0134      */
0135     pci_write_config_byte(dev, 0x44, 0x30 | ULI_8259_IRQ14);
0136     pci_write_config_byte(dev, 0x75, ULI_8259_IRQ15);
0137 }
0138
0139 static void quirk_final_uli1575(struct pci_dev *dev)
0140 {
0141     /* Set i8259 interrupt trigger
0142      * IRQ 3:  Level
0143      * IRQ 4:  Level
0144      * IRQ 5:  Level
0145      * IRQ 6:  Level
0146      * IRQ 7:  Level
0147      * IRQ 9:  Level
0148      * IRQ 10: Level
0149      * IRQ 11: Level
0150      * IRQ 12: Level
0151      * IRQ 14: Edge
0152      * IRQ 15: Edge
0153      */
0154     if (!is_quirk_valid())
0155         return;
0156
0157     outb(0xfa, 0x4d0);
0158     outb(0x1e, 0x4d1);
0159
0160     /* setup RTC */
0161     CMOS_WRITE(RTC_SET, RTC_CONTROL);
0162     CMOS_WRITE(RTC_24H, RTC_CONTROL);
0163
0164     /* ensure month, date, and week alarm fields are ignored */
0165     CMOS_WRITE(0, RTC_VALID);
0166
0167     outb_p(0x7c, 0x72);
0168     outb_p(RTC_ALARM_DONT_CARE, 0x73);
0169
0170     outb_p(0x7d, 0x72);
0171     outb_p(RTC_ALARM_DONT_CARE, 0x73);
0172 }
0173
0174 /* SATA */
0175 static void quirk_uli5288(struct pci_dev *dev)
0176 {
0177     unsigned char c;
0178     unsigned int d;
0179
0180     if (!is_quirk_valid())
0181         return;
0182
0183     /* read/write lock */
0184     pci_read_config_byte(dev, 0x83, &c);
0185     pci_write_config_byte(dev, 0x83, c|0x80);
0186
0187     pci_read_config_dword(dev, PCI_CLASS_REVISION, &d);
0188     d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8);
0189     pci_write_config_dword(dev, PCI_CLASS_REVISION, d);
0190
0191     /* restore lock */
0192     pci_write_config_byte(dev, 0x83, c);
0193
0194     /* disable emulated PATA mode enabled */
0195     pci_read_config_byte(dev, 0x84, &c);
0196     pci_write_config_byte(dev, 0x84, c & ~0x01);
0197 }
0198
0199 /* PATA */
0200 static void quirk_uli5229(struct pci_dev *dev)
0201 {
0202     unsigned short temp;
0203
0204     if (!is_quirk_valid())
0205         return;
0206
0207     pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE |
0208         PCI_COMMAND_MASTER | PCI_COMMAND_IO);
0209
0210     /* Enable Native IRQ 14/15 */
0211     pci_read_config_word(dev, 0x4a, &temp);
0212     pci_write_config_word(dev, 0x4a, temp | 0x1000);
0213 }
0214
0215 /* We have to do a dummy read on the P2P for the RTC to work, WTF */
0216 static void quirk_final_uli5249(struct pci_dev *dev)
0217 {
0218     int i;
0219     u8 *dummy;
0220     struct pci_bus *bus = dev->bus;
0221     struct resource *res;
0222     resource_size_t end = 0;
0223
0224     for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCES+3; i++) {
0225         unsigned long flags = pci_resource_flags(dev, i);
0226         if ((flags & (IORESOURCE_MEM|IORESOURCE_PREFETCH)) == IORESOURCE_MEM)
0227             end = pci_resource_end(dev, i);
0228     }
0229
0230     pci_bus_for_each_resource(bus, res, i) {
0231         if (res && res->flags & IORESOURCE_MEM) {
0232             if (res->end == end)
0233                 dummy = ioremap(res->start, 0x4);
0234             else
0235                 dummy = ioremap(res->end - 3, 0x4);
0236             if (dummy) {
0237                 in_8(dummy);
0238                 iounmap(dummy);
0239             }
0240             break;
0241         }
0242     }
0243 }
0244
0245 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
0246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
0247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
0248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
0249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249);
0250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575);
0251 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
0252
0253 static void hpcd_quirk_uli1575(struct pci_dev *dev)
0254 {
0255     u32 temp32;
0256
0257     if (!machine_is(mpc86xx_hpcd))
0258         return;
0259
0260     /* Disable INTx */
0261     pci_read_config_dword(dev, 0x48, &temp32);
0262     pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
0263
0264     /* Enable sideband interrupt */
0265     pci_read_config_dword(dev, 0x90, &temp32);
0266     pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
0267 }
0268
0269 static void hpcd_quirk_uli5288(struct pci_dev *dev)
0270 {
0271     unsigned char c;
0272
0273     if (!machine_is(mpc86xx_hpcd))
0274         return;
0275
0276     pci_read_config_byte(dev, 0x83, &c);
0277     c |= 0x80;
0278     pci_write_config_byte(dev, 0x83, c);
0279
0280     pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
0281     pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
0282
0283     pci_read_config_byte(dev, 0x83, &c);
0284     c &= 0x7f;
0285     pci_write_config_byte(dev, 0x83, c);
0286 }
0287
0288 /*
0289  * Since 8259PIC was disabled on the board, the IDE device can not
0290  * use the legacy IRQ, we need to let the IDE device work under
0291  * native mode and use the interrupt line like other PCI devices.
0292  * IRQ14 is a sideband interrupt from IDE device to CPU and we use this
0293  * as the interrupt for IDE device.
0294  */
0295 static void hpcd_quirk_uli5229(struct pci_dev *dev)
0296 {
0297     unsigned char c;
0298
0299     if (!machine_is(mpc86xx_hpcd))
0300         return;
0301
0302     pci_read_config_byte(dev, 0x4b, &c);
0303     c |= 0x10;
0304     pci_write_config_byte(dev, 0x4b, c);
0305 }
0306
0307 /*
0308  * SATA interrupt pin bug fix
0309  * There's a chip bug for 5288, The interrupt pin should be 2,
0310  * not the read only value 1, So it use INTB#, not INTA# which
0311  * actually used by the IDE device 5229.
0312  * As of this bug, during the PCI initialization, 5288 read the
0313  * irq of IDE device from the device tree, this function fix this
0314  * bug by re-assigning a correct irq to 5288.
0315  *
0316  */
0317 static void hpcd_final_uli5288(struct pci_dev *dev)
0318 {
0319     struct pci_controller *hose = pci_bus_to_host(dev->bus);
0320     struct device_node *hosenode = hose ? hose->dn : NULL;
0321     struct of_phandle_args oirq;
0322     u32 laddr[3];
0323
0324     if (!machine_is(mpc86xx_hpcd))
0325         return;
0326
0327     if (!hosenode)
0328         return;
0329
0330     oirq.np = hosenode;
0331     oirq.args[0] = 2;
0332     oirq.args_count = 1;
0333     laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
0334     laddr[1] = laddr[2] = 0;
0335     of_irq_parse_raw(laddr, &oirq);
0336     dev->irq = irq_create_of_mapping(&oirq);
0337 }
0338
0339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575);
0340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288);
0341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229);
0342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288);
0343
0344 int uli_exclude_device(struct pci_controller *hose,
0345             u_char bus, u_char devfn)
0346 {
0347     if (bus == (hose->first_busno + 2)) {
0348         /* exclude Modem controller */
0349         if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1))
0350             return PCIBIOS_DEVICE_NOT_FOUND;
0351
0352         /* exclude HD Audio controller */
0353         if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2))
0354             return PCIBIOS_DEVICE_NOT_FOUND;
0355     }
0356
0357     return PCIBIOS_SUCCESSFUL;
0358 }