platforms/embedded6xx/mpc10x.h

0001 /*
0002  * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
0003  * ctlr/EPIC/etc.
0004  *
0005  * Author: Mark A. Greer
0006  *         mgreer@mvista.com
0007  *
0008  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
0009  * the terms of the GNU General Public License version 2.  This program
0010  * is licensed "as is" without any warranty of any kind, whether express
0011  * or implied.
0012  */
0013 #ifndef __PPC_KERNEL_MPC10X_H
0014 #define __PPC_KERNEL_MPC10X_H
0015
0016 #include <linux/pci_ids.h>
0017 #include <asm/pci-bridge.h>
0018
0019 /*
0020  * The values here don't completely map everything but should work in most
0021  * cases.
0022  *
0023  * MAP A (PReP Map)
0024  *   Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
0025  *   Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
0026  *   PCI MEM:   0x80000000 -> Processor System Memory: 0x00000000
0027  *
0028  * MAP B (CHRP Map)
0029  *   Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
0030  *   Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
0031  *   PCI MEM:   0x00000000 -> Processor System Memory: 0x00000000
0032  */
0033
0034 /*
0035  * Define the vendor/device IDs for the various bridges--should be added to
0036  * <linux/pci_ids.h>
0037  */
0038 #define MPC10X_BRIDGE_106   ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) |  \
0039                   PCI_VENDOR_ID_MOTOROLA)
0040 #define MPC10X_BRIDGE_8240  ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
0041 #define MPC10X_BRIDGE_107   ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
0042 #define MPC10X_BRIDGE_8245  ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
0043
0044 /* Define the type of map to use */
0045 #define MPC10X_MEM_MAP_A        1
0046 #define MPC10X_MEM_MAP_B        2
0047
0048 /* Map A (PReP Map) Defines */
0049 #define MPC10X_MAPA_CNFG_ADDR       0x80000cf8
0050 #define MPC10X_MAPA_CNFG_DATA       0x80000cfc
0051
0052 #define MPC10X_MAPA_ISA_IO_BASE     0x80000000
0053 #define MPC10X_MAPA_ISA_MEM_BASE    0xc0000000
0054 #define MPC10X_MAPA_DRAM_OFFSET     0x80000000
0055
0056 #define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0
0057 #define MPC10X_MAPA_PCI_IO_START    0x00000000
0058 #define MPC10X_MAPA_PCI_IO_END         (0x00800000 - 1)
0059 #define MPC10X_MAPA_PCI_MEM_START   0x00000000
0060 #define MPC10X_MAPA_PCI_MEM_END        (0x20000000 - 1)
0061
0062 #define MPC10X_MAPA_PCI_MEM_OFFSET  (MPC10X_MAPA_ISA_MEM_BASE - \
0063                      MPC10X_MAPA_PCI_MEM_START)
0064
0065 /* Map B (CHRP Map) Defines */
0066 #define MPC10X_MAPB_CNFG_ADDR       0xfec00000
0067 #define MPC10X_MAPB_CNFG_DATA       0xfee00000
0068
0069 #define MPC10X_MAPB_ISA_IO_BASE     0xfe000000
0070 #define MPC10X_MAPB_ISA_MEM_BASE    0x80000000
0071 #define MPC10X_MAPB_DRAM_OFFSET     0x00000000
0072
0073 #define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000
0074 #define MPC10X_MAPB_PCI_IO_START    0x00000000
0075 #define MPC10X_MAPB_PCI_IO_END         (0x00c00000 - 1)
0076 #define MPC10X_MAPB_PCI_MEM_START   0x80000000
0077 #define MPC10X_MAPB_PCI_MEM_END        (0xc0000000 - 1)
0078
0079 #define MPC10X_MAPB_PCI_MEM_OFFSET  (MPC10X_MAPB_ISA_MEM_BASE - \
0080                      MPC10X_MAPB_PCI_MEM_START)
0081
0082 /* Miscellaneous Configuration register offsets */
0083 #define MPC10X_CFG_PIR_REG      0x09
0084 #define MPC10X_CFG_PIR_HOST_BRIDGE  0x00
0085 #define MPC10X_CFG_PIR_AGENT        0x01
0086
0087 #define MPC10X_CFG_EUMBBAR      0x78
0088
0089 #define MPC10X_CFG_PICR1_REG        0xa8
0090 #define MPC10X_CFG_PICR1_ADDR_MAP_MASK  0x00010000
0091 #define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000
0092 #define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000
0093 #define MPC10X_CFG_PICR1_SPEC_PCI_RD    0x00000004
0094 #define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040
0095
0096 #define MPC10X_CFG_PICR2_REG        0xac
0097 #define MPC10X_CFG_PICR2_COPYBACK_OPT   0x00000001
0098
0099 #define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0
0100 #define MPC10X_CFG_MAPB_OPTIONS_CFAE    0x80    /* CPU_FD_ALIAS_EN */
0101 #define MPC10X_CFG_MAPB_OPTIONS_PFAE    0x40    /* PCI_FD_ALIAS_EN */
0102 #define MPC10X_CFG_MAPB_OPTIONS_DR  0x20    /* DLL_RESET */
0103 #define MPC10X_CFG_MAPB_OPTIONS_PCICH   0x08    /* PCI_COMPATIBILITY_HOLE */
0104 #define MPC10X_CFG_MAPB_OPTIONS_PROCCH  0x04    /* PROC_COMPATIBILITY_HOLE */
0105
0106 /* Define offsets for the memory controller registers in the config space */
0107 #define MPC10X_MCTLR_MEM_START_1    0x80    /* Banks 0-3 */
0108 #define MPC10X_MCTLR_MEM_START_2    0x84    /* Banks 4-7 */
0109 #define MPC10X_MCTLR_EXT_MEM_START_1    0x88    /* Banks 0-3 */
0110 #define MPC10X_MCTLR_EXT_MEM_START_2    0x8c    /* Banks 4-7 */
0111
0112 #define MPC10X_MCTLR_MEM_END_1      0x90    /* Banks 0-3 */
0113 #define MPC10X_MCTLR_MEM_END_2      0x94    /* Banks 4-7 */
0114 #define MPC10X_MCTLR_EXT_MEM_END_1  0x98    /* Banks 0-3 */
0115 #define MPC10X_MCTLR_EXT_MEM_END_2  0x9c    /* Banks 4-7 */
0116
0117 #define MPC10X_MCTLR_MEM_BANK_ENABLES   0xa0
0118
0119 /* Define some offset in the EUMB */
0120 #define MPC10X_EUMB_SIZE        0x00100000 /* Total EUMB size (1MB) */
0121
0122 #define MPC10X_EUMB_MU_OFFSET       0x00000000 /* Msg Unit reg offset */
0123 #define MPC10X_EUMB_MU_SIZE     0x00001000 /* Msg Unit reg size */
0124 #define MPC10X_EUMB_DMA_OFFSET      0x00001000 /* DMA Unit reg offset */
0125 #define MPC10X_EUMB_DMA_SIZE        0x00001000 /* DMA Unit reg size  */
0126 #define MPC10X_EUMB_ATU_OFFSET      0x00002000 /* Addr xlate reg offset */
0127 #define MPC10X_EUMB_ATU_SIZE        0x00001000 /* Addr xlate reg size  */
0128 #define MPC10X_EUMB_I2C_OFFSET      0x00003000 /* I2C Unit reg offset */
0129 #define MPC10X_EUMB_I2C_SIZE        0x00001000 /* I2C Unit reg size  */
0130 #define MPC10X_EUMB_DUART_OFFSET    0x00004000 /* DUART Unit reg offset (8245) */
0131 #define MPC10X_EUMB_DUART_SIZE      0x00001000 /* DUART Unit reg size (8245) */
0132 #define MPC10X_EUMB_EPIC_OFFSET     0x00040000 /* EPIC offset in EUMB */
0133 #define MPC10X_EUMB_EPIC_SIZE       0x00030000 /* EPIC size */
0134 #define MPC10X_EUMB_PM_OFFSET       0x000fe000 /* Performance Monitor reg offset (8245) */
0135 #define MPC10X_EUMB_PM_SIZE     0x00001000 /* Performance Monitor reg size (8245) */
0136 #define MPC10X_EUMB_WP_OFFSET       0x000ff000 /* Data path diagnostic, watchpoint reg offset */
0137 #define MPC10X_EUMB_WP_SIZE     0x00001000 /* Data path diagnostic, watchpoint reg size */
0138
0139 enum ppc_sys_devices {
0140     MPC10X_IIC1,
0141     MPC10X_DMA0,
0142     MPC10X_DMA1,
0143     MPC10X_UART0,
0144     MPC10X_UART1,
0145     NUM_PPC_SYS_DEVS,
0146 };
0147
0148 int mpc10x_bridge_init(struct pci_controller *hose,
0149                uint current_map,
0150                uint new_map,
0151                uint phys_eumb_base);
0152 unsigned long mpc10x_get_mem_size(uint mem_map);
0153 int mpc10x_enable_store_gathering(struct pci_controller *hose);
0154 int mpc10x_disable_store_gathering(struct pci_controller *hose);
0155
0156 /* For MPC107 boards that use the built-in openpic */
0157 void mpc10x_set_openpic(void);
0158
0159 #endif  /* __PPC_KERNEL_MPC10X_H */