platforms/chrp/pegasos_eth.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
0004  *  Thanks to :
0005  *  Dale Farnsworth <dale@farnsworth.org>
0006  *  Mark A. Greer <mgreer@mvista.com>
0007  *  Nicolas DET <nd@bplan-gmbh.de>
0008  *  Benjamin Herrenschmidt <benh@kernel.crashing.org>
0009  *  And anyone else who helped me on this.
0010  */
0011
0012 #include <linux/types.h>
0013 #include <linux/init.h>
0014 #include <linux/ioport.h>
0015 #include <linux/device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/mv643xx.h>
0018 #include <linux/pci.h>
0019
0020 #define PEGASOS2_MARVELL_REGBASE        (0xf1000000)
0021 #define PEGASOS2_MARVELL_REGSIZE        (0x00004000)
0022 #define PEGASOS2_SRAM_BASE          (0xf2000000)
0023 #define PEGASOS2_SRAM_SIZE          (256*1024)
0024
0025 #define PEGASOS2_SRAM_BASE_ETH_PORT0            (PEGASOS2_SRAM_BASE)
0026 #define PEGASOS2_SRAM_BASE_ETH_PORT1            (PEGASOS2_SRAM_BASE_ETH_PORT0 + (PEGASOS2_SRAM_SIZE / 2) )
0027
0028
0029 #define PEGASOS2_SRAM_RXRING_SIZE       (PEGASOS2_SRAM_SIZE/4)
0030 #define PEGASOS2_SRAM_TXRING_SIZE       (PEGASOS2_SRAM_SIZE/4)
0031
0032 #undef BE_VERBOSE
0033
0034 static struct resource mv643xx_eth_shared_resources[] = {
0035     [0] = {
0036         .name   = "ethernet shared base",
0037         .start  = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
0038         .end    = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
0039                     MV643XX_ETH_SHARED_REGS_SIZE - 1,
0040         .flags  = IORESOURCE_MEM,
0041     },
0042 };
0043
0044 static struct platform_device mv643xx_eth_shared_device = {
0045     .name       = MV643XX_ETH_SHARED_NAME,
0046     .id     = 0,
0047     .num_resources  = ARRAY_SIZE(mv643xx_eth_shared_resources),
0048     .resource   = mv643xx_eth_shared_resources,
0049 };
0050
0051 /*
0052  * The orion mdio driver only covers shared + 0x4 up to shared + 0x84 - 1
0053  */
0054 static struct resource mv643xx_eth_mvmdio_resources[] = {
0055     [0] = {
0056         .name   = "ethernet mdio base",
0057         .start  = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x4,
0058         .end    = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x83,
0059         .flags  = IORESOURCE_MEM,
0060     },
0061 };
0062
0063 static struct platform_device mv643xx_eth_mvmdio_device = {
0064     .name       = "orion-mdio",
0065     .id     = -1,
0066     .num_resources  = ARRAY_SIZE(mv643xx_eth_mvmdio_resources),
0067     .resource   = mv643xx_eth_mvmdio_resources,
0068 };
0069
0070 static struct resource mv643xx_eth_port1_resources[] = {
0071     [0] = {
0072         .name   = "eth port1 irq",
0073         .start  = 9,
0074         .end    = 9,
0075         .flags  = IORESOURCE_IRQ,
0076     },
0077 };
0078
0079 static struct mv643xx_eth_platform_data eth_port1_pd = {
0080     .shared     = &mv643xx_eth_shared_device,
0081     .port_number    = 1,
0082     .phy_addr   = MV643XX_ETH_PHY_ADDR(7),
0083
0084     .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1,
0085     .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
0086     .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
0087
0088     .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1 + PEGASOS2_SRAM_TXRING_SIZE,
0089     .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
0090     .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
0091 };
0092
0093 static struct platform_device eth_port1_device = {
0094     .name       = MV643XX_ETH_NAME,
0095     .id     = 1,
0096     .num_resources  = ARRAY_SIZE(mv643xx_eth_port1_resources),
0097     .resource   = mv643xx_eth_port1_resources,
0098     .dev = {
0099         .platform_data = &eth_port1_pd,
0100     },
0101 };
0102
0103 static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
0104     &mv643xx_eth_shared_device,
0105     &mv643xx_eth_mvmdio_device,
0106     &eth_port1_device,
0107 };
0108
0109 /***********/
0110 /***********/
0111 #define MV_READ(offset,val)     { val = readl(mv643xx_reg_base + offset); }
0112 #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
0113
0114 static void __iomem *mv643xx_reg_base;
0115
0116 static int __init Enable_SRAM(void)
0117 {
0118     u32 ALong;
0119
0120     if (mv643xx_reg_base == NULL)
0121         mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
0122                     PEGASOS2_MARVELL_REGSIZE);
0123
0124     if (mv643xx_reg_base == NULL)
0125         return -ENOMEM;
0126
0127 #ifdef BE_VERBOSE
0128     printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
0129         (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
0130 #endif
0131
0132     MV_WRITE(MV64340_SRAM_CONFIG, 0);
0133
0134     MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
0135
0136     MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
0137     ALong &= ~(1 << 19);
0138     MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
0139
0140     ALong = 0x02;
0141     ALong |= PEGASOS2_SRAM_BASE & 0xffff0000;
0142     MV_WRITE(MV643XX_ETH_BAR_4, ALong);
0143
0144     MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);
0145
0146     MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
0147     ALong &= ~(1 << 4);
0148     MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
0149
0150 #ifdef BE_VERBOSE
0151     printk("Pegasos II/Marvell MV64361: register unmapped\n");
0152     printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
0153 #endif
0154
0155     iounmap(mv643xx_reg_base);
0156     mv643xx_reg_base = NULL;
0157
0158     return 1;
0159 }
0160
0161
0162 /***********/
0163 /***********/
0164 static int __init mv643xx_eth_add_pds(void)
0165 {
0166     int ret = 0;
0167     static struct pci_device_id pci_marvell_mv64360[] = {
0168         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
0169         { }
0170     };
0171
0172 #ifdef BE_VERBOSE
0173     printk("Pegasos II/Marvell MV64361: init\n");
0174 #endif
0175
0176     if (pci_dev_present(pci_marvell_mv64360)) {
0177         ret = platform_add_devices(mv643xx_eth_pd_devs,
0178                 ARRAY_SIZE(mv643xx_eth_pd_devs));
0179
0180         if ( Enable_SRAM() < 0)
0181         {
0182             eth_port1_pd.tx_sram_addr = 0;
0183             eth_port1_pd.tx_sram_size = 0;
0184             eth_port1_pd.rx_sram_addr = 0;
0185             eth_port1_pd.rx_sram_size = 0;
0186
0187 #ifdef BE_VERBOSE
0188             printk("Pegasos II/Marvell MV64361: Can't enable the "
0189                 "SRAM\n");
0190 #endif
0191         }
0192     }
0193
0194 #ifdef BE_VERBOSE
0195     printk("Pegasos II/Marvell MV64361: init is over\n");
0196 #endif
0197
0198     return ret;
0199 }
0200
0201 device_initcall(mv643xx_eth_add_pds);