platforms/chrp/gg2.h

0001 /*
0002  *  include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
0003  *
0004  *  Copyright (C) 1997 Geert Uytterhoeven
0005  *
0006  *  This file is based on the following documentation:
0007  *
0008  *  The VAS96011/12 Chipset, Data Book, Edition 1.0
0009  *  VLSI Technology, Inc.
0010  *
0011  *  This file is subject to the terms and conditions of the GNU General Public
0012  *  License.  See the file COPYING in the main directory of this archive
0013  *  for more details.
0014  */
0015
0016 #ifndef _ASMPPC_GG2_H
0017 #define _ASMPPC_GG2_H
0018
0019     /*
0020      *  Memory Map (CHRP mode)
0021      */
0022
0023 #define GG2_PCI_MEM_BASE    0xc0000000  /* Peripheral memory space */
0024 #define GG2_ISA_MEM_BASE    0xf7000000  /* Peripheral memory alias */
0025 #define GG2_ISA_IO_BASE     0xf8000000  /* Peripheral I/O space */
0026 #define GG2_PCI_CONFIG_BASE 0xfec00000  /* PCI configuration space */
0027 #define GG2_INT_ACK_SPECIAL 0xfec80000  /* Interrupt acknowledge and */
0028                         /* special PCI cycles */
0029 #define GG2_ROM_BASE0       0xff000000  /* ROM bank 0 */
0030 #define GG2_ROM_BASE1       0xff800000  /* ROM bank 1 */
0031
0032
0033     /*
0034      *  GG2 specific PCI Registers
0035      */
0036
0037 extern void __iomem *gg2_pci_config_base;   /* kernel virtual address */
0038
0039 #define GG2_PCI_BUSNO       0x40    /* Bus number */
0040 #define GG2_PCI_SUBBUSNO    0x41    /* Subordinate bus number */
0041 #define GG2_PCI_DISCCTR     0x42    /* Disconnect counter */
0042 #define GG2_PCI_PPC_CTRL    0x50    /* PowerPC interface control register */
0043 #define GG2_PCI_ADDR_MAP    0x5c    /* Address map */
0044 #define GG2_PCI_PCI_CTRL    0x60    /* PCI interface control register */
0045 #define GG2_PCI_ROM_CTRL    0x70    /* ROM interface control register */
0046 #define GG2_PCI_ROM_TIME    0x74    /* ROM timing */
0047 #define GG2_PCI_CC_CTRL     0x80    /* Cache controller control register */
0048 #define GG2_PCI_DRAM_BANK0  0x90    /* Control register for DRAM bank #0 */
0049 #define GG2_PCI_DRAM_BANK1  0x94    /* Control register for DRAM bank #1 */
0050 #define GG2_PCI_DRAM_BANK2  0x98    /* Control register for DRAM bank #2 */
0051 #define GG2_PCI_DRAM_BANK3  0x9c    /* Control register for DRAM bank #3 */
0052 #define GG2_PCI_DRAM_BANK4  0xa0    /* Control register for DRAM bank #4 */
0053 #define GG2_PCI_DRAM_BANK5  0xa4    /* Control register for DRAM bank #5 */
0054 #define GG2_PCI_DRAM_TIME0  0xb0    /* Timing parameters set #0 */
0055 #define GG2_PCI_DRAM_TIME1  0xb4    /* Timing parameters set #1 */
0056 #define GG2_PCI_DRAM_CTRL   0xc0    /* DRAM control */
0057 #define GG2_PCI_ERR_CTRL    0xd0    /* Error control register */
0058 #define GG2_PCI_ERR_STATUS  0xd4    /* Error status register */
0059                     /* Cleared when read */
0060
0061 #endif /* _ASMPPC_GG2_H */