cell/spufs/spu_restore.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * spu_restore.c
0004  *
0005  * (C) Copyright IBM Corp. 2005
0006  *
0007  * SPU-side context restore sequence outlined in
0008  * Synergistic Processor Element Book IV
0009  *
0010  * Author: Mark Nutter <mnutter@us.ibm.com>
0011  */
0012
0013
0014 #ifndef LS_SIZE
0015 #define LS_SIZE                 0x40000 /* 256K (in bytes) */
0016 #endif
0017
0018 typedef unsigned int u32;
0019 typedef unsigned long long u64;
0020
0021 #include <spu_intrinsics.h>
0022 #include <asm/spu_csa.h>
0023 #include "spu_utils.h"
0024
0025 #define BR_INSTR        0x327fff80  /* br -4         */
0026 #define NOP_INSTR       0x40200000  /* nop           */
0027 #define HEQ_INSTR       0x7b000000  /* heq $0, $0    */
0028 #define STOP_INSTR      0x00000000  /* stop 0x0      */
0029 #define ILLEGAL_INSTR       0x00800000  /* illegal instr */
0030 #define RESTORE_COMPLETE    0x00003ffc  /* stop 0x3ffc   */
0031
0032 static inline void fetch_regs_from_mem(addr64 lscsa_ea)
0033 {
0034     unsigned int ls = (unsigned int)&regs_spill[0];
0035     unsigned int size = sizeof(regs_spill);
0036     unsigned int tag_id = 0;
0037     unsigned int cmd = 0x40;    /* GET */
0038
0039     spu_writech(MFC_LSA, ls);
0040     spu_writech(MFC_EAH, lscsa_ea.ui[0]);
0041     spu_writech(MFC_EAL, lscsa_ea.ui[1]);
0042     spu_writech(MFC_Size, size);
0043     spu_writech(MFC_TagID, tag_id);
0044     spu_writech(MFC_Cmd, cmd);
0045 }
0046
0047 static inline void restore_upper_240kb(addr64 lscsa_ea)
0048 {
0049     unsigned int ls = 16384;
0050     unsigned int list = (unsigned int)&dma_list[0];
0051     unsigned int size = sizeof(dma_list);
0052     unsigned int tag_id = 0;
0053     unsigned int cmd = 0x44;    /* GETL */
0054
0055     /* Restore, Step 4:
0056      *    Enqueue the GETL command (tag 0) to the MFC SPU command
0057      *    queue to transfer the upper 240 kb of LS from CSA.
0058      */
0059     spu_writech(MFC_LSA, ls);
0060     spu_writech(MFC_EAH, lscsa_ea.ui[0]);
0061     spu_writech(MFC_EAL, list);
0062     spu_writech(MFC_Size, size);
0063     spu_writech(MFC_TagID, tag_id);
0064     spu_writech(MFC_Cmd, cmd);
0065 }
0066
0067 static inline void restore_decr(void)
0068 {
0069     unsigned int offset;
0070     unsigned int decr_running;
0071     unsigned int decr;
0072
0073     /* Restore, Step 6(moved):
0074      *    If the LSCSA "decrementer running" flag is set
0075      *    then write the SPU_WrDec channel with the
0076      *    decrementer value from LSCSA.
0077      */
0078     offset = LSCSA_QW_OFFSET(decr_status);
0079     decr_running = regs_spill[offset].slot[0] & SPU_DECR_STATUS_RUNNING;
0080     if (decr_running) {
0081         offset = LSCSA_QW_OFFSET(decr);
0082         decr = regs_spill[offset].slot[0];
0083         spu_writech(SPU_WrDec, decr);
0084     }
0085 }
0086
0087 static inline void write_ppu_mb(void)
0088 {
0089     unsigned int offset;
0090     unsigned int data;
0091
0092     /* Restore, Step 11:
0093      *    Write the MFC_WrOut_MB channel with the PPU_MB
0094      *    data from LSCSA.
0095      */
0096     offset = LSCSA_QW_OFFSET(ppu_mb);
0097     data = regs_spill[offset].slot[0];
0098     spu_writech(SPU_WrOutMbox, data);
0099 }
0100
0101 static inline void write_ppuint_mb(void)
0102 {
0103     unsigned int offset;
0104     unsigned int data;
0105
0106     /* Restore, Step 12:
0107      *    Write the MFC_WrInt_MB channel with the PPUINT_MB
0108      *    data from LSCSA.
0109      */
0110     offset = LSCSA_QW_OFFSET(ppuint_mb);
0111     data = regs_spill[offset].slot[0];
0112     spu_writech(SPU_WrOutIntrMbox, data);
0113 }
0114
0115 static inline void restore_fpcr(void)
0116 {
0117     unsigned int offset;
0118     vector unsigned int fpcr;
0119
0120     /* Restore, Step 13:
0121      *    Restore the floating-point status and control
0122      *    register from the LSCSA.
0123      */
0124     offset = LSCSA_QW_OFFSET(fpcr);
0125     fpcr = regs_spill[offset].v;
0126     spu_mtfpscr(fpcr);
0127 }
0128
0129 static inline void restore_srr0(void)
0130 {
0131     unsigned int offset;
0132     unsigned int srr0;
0133
0134     /* Restore, Step 14:
0135      *    Restore the SPU SRR0 data from the LSCSA.
0136      */
0137     offset = LSCSA_QW_OFFSET(srr0);
0138     srr0 = regs_spill[offset].slot[0];
0139     spu_writech(SPU_WrSRR0, srr0);
0140 }
0141
0142 static inline void restore_event_mask(void)
0143 {
0144     unsigned int offset;
0145     unsigned int event_mask;
0146
0147     /* Restore, Step 15:
0148      *    Restore the SPU_RdEventMsk data from the LSCSA.
0149      */
0150     offset = LSCSA_QW_OFFSET(event_mask);
0151     event_mask = regs_spill[offset].slot[0];
0152     spu_writech(SPU_WrEventMask, event_mask);
0153 }
0154
0155 static inline void restore_tag_mask(void)
0156 {
0157     unsigned int offset;
0158     unsigned int tag_mask;
0159
0160     /* Restore, Step 16:
0161      *    Restore the SPU_RdTagMsk data from the LSCSA.
0162      */
0163     offset = LSCSA_QW_OFFSET(tag_mask);
0164     tag_mask = regs_spill[offset].slot[0];
0165     spu_writech(MFC_WrTagMask, tag_mask);
0166 }
0167
0168 static inline void restore_complete(void)
0169 {
0170     extern void exit_fini(void);
0171     unsigned int *exit_instrs = (unsigned int *)exit_fini;
0172     unsigned int offset;
0173     unsigned int stopped_status;
0174     unsigned int stopped_code;
0175
0176     /* Restore, Step 18:
0177      *    Issue a stop-and-signal instruction with
0178      *    "good context restore" signal value.
0179      *
0180      * Restore, Step 19:
0181      *    There may be additional instructions placed
0182      *    here by the PPE Sequence for SPU Context
0183      *    Restore in order to restore the correct
0184      *    "stopped state".
0185      *
0186      *    This step is handled here by analyzing the
0187      *    LSCSA.stopped_status and then modifying the
0188      *    exit() function to behave appropriately.
0189      */
0190
0191     offset = LSCSA_QW_OFFSET(stopped_status);
0192     stopped_status = regs_spill[offset].slot[0];
0193     stopped_code = regs_spill[offset].slot[1];
0194
0195     switch (stopped_status) {
0196     case SPU_STOPPED_STATUS_P_I:
0197         /* SPU_Status[P,I]=1.  Add illegal instruction
0198          * followed by stop-and-signal instruction after
0199          * end of restore code.
0200          */
0201         exit_instrs[0] = RESTORE_COMPLETE;
0202         exit_instrs[1] = ILLEGAL_INSTR;
0203         exit_instrs[2] = STOP_INSTR | stopped_code;
0204         break;
0205     case SPU_STOPPED_STATUS_P_H:
0206         /* SPU_Status[P,H]=1.  Add 'heq $0, $0' followed
0207          * by stop-and-signal instruction after end of
0208          * restore code.
0209          */
0210         exit_instrs[0] = RESTORE_COMPLETE;
0211         exit_instrs[1] = HEQ_INSTR;
0212         exit_instrs[2] = STOP_INSTR | stopped_code;
0213         break;
0214     case SPU_STOPPED_STATUS_S_P:
0215         /* SPU_Status[S,P]=1.  Add nop instruction
0216          * followed by 'br -4' after end of restore
0217          * code.
0218          */
0219         exit_instrs[0] = RESTORE_COMPLETE;
0220         exit_instrs[1] = STOP_INSTR | stopped_code;
0221         exit_instrs[2] = NOP_INSTR;
0222         exit_instrs[3] = BR_INSTR;
0223         break;
0224     case SPU_STOPPED_STATUS_S_I:
0225         /* SPU_Status[S,I]=1.  Add  illegal instruction
0226          * followed by 'br -4' after end of restore code.
0227          */
0228         exit_instrs[0] = RESTORE_COMPLETE;
0229         exit_instrs[1] = ILLEGAL_INSTR;
0230         exit_instrs[2] = NOP_INSTR;
0231         exit_instrs[3] = BR_INSTR;
0232         break;
0233     case SPU_STOPPED_STATUS_I:
0234         /* SPU_Status[I]=1. Add illegal instruction followed
0235          * by infinite loop after end of restore sequence.
0236          */
0237         exit_instrs[0] = RESTORE_COMPLETE;
0238         exit_instrs[1] = ILLEGAL_INSTR;
0239         exit_instrs[2] = NOP_INSTR;
0240         exit_instrs[3] = BR_INSTR;
0241         break;
0242     case SPU_STOPPED_STATUS_S:
0243         /* SPU_Status[S]=1. Add two 'nop' instructions. */
0244         exit_instrs[0] = RESTORE_COMPLETE;
0245         exit_instrs[1] = NOP_INSTR;
0246         exit_instrs[2] = NOP_INSTR;
0247         exit_instrs[3] = BR_INSTR;
0248         break;
0249     case SPU_STOPPED_STATUS_H:
0250         /* SPU_Status[H]=1. Add 'heq $0, $0' instruction
0251          * after end of restore code.
0252          */
0253         exit_instrs[0] = RESTORE_COMPLETE;
0254         exit_instrs[1] = HEQ_INSTR;
0255         exit_instrs[2] = NOP_INSTR;
0256         exit_instrs[3] = BR_INSTR;
0257         break;
0258     case SPU_STOPPED_STATUS_P:
0259         /* SPU_Status[P]=1. Add stop-and-signal instruction
0260          * after end of restore code.
0261          */
0262         exit_instrs[0] = RESTORE_COMPLETE;
0263         exit_instrs[1] = STOP_INSTR | stopped_code;
0264         break;
0265     case SPU_STOPPED_STATUS_R:
0266         /* SPU_Status[I,S,H,P,R]=0. Add infinite loop. */
0267         exit_instrs[0] = RESTORE_COMPLETE;
0268         exit_instrs[1] = NOP_INSTR;
0269         exit_instrs[2] = NOP_INSTR;
0270         exit_instrs[3] = BR_INSTR;
0271         break;
0272     default:
0273         /* SPU_Status[R]=1. No additional instructions. */
0274         break;
0275     }
0276     spu_sync();
0277 }
0278
0279 /**
0280  * main - entry point for SPU-side context restore.
0281  *
0282  * This code deviates from the documented sequence in the
0283  * following aspects:
0284  *
0285  *  1. The EA for LSCSA is passed from PPE in the
0286  *     signal notification channels.
0287  *  2. The register spill area is pulled by SPU
0288  *     into LS, rather than pushed by PPE.
0289  *  3. All 128 registers are restored by exit().
0290  *  4. The exit() function is modified at run
0291  *     time in order to properly restore the
0292  *     SPU_Status register.
0293  */
0294 int main()
0295 {
0296     addr64 lscsa_ea;
0297
0298     lscsa_ea.ui[0] = spu_readch(SPU_RdSigNotify1);
0299     lscsa_ea.ui[1] = spu_readch(SPU_RdSigNotify2);
0300     fetch_regs_from_mem(lscsa_ea);
0301
0302     set_event_mask();       /* Step 1.  */
0303     set_tag_mask();         /* Step 2.  */
0304     build_dma_list(lscsa_ea);   /* Step 3.  */
0305     restore_upper_240kb(lscsa_ea);  /* Step 4.  */
0306                     /* Step 5: done by 'exit'. */
0307     enqueue_putllc(lscsa_ea);   /* Step 7. */
0308     set_tag_update();       /* Step 8. */
0309     read_tag_status();      /* Step 9. */
0310     restore_decr();         /* moved Step 6. */
0311     read_llar_status();     /* Step 10. */
0312     write_ppu_mb();         /* Step 11. */
0313     write_ppuint_mb();      /* Step 12. */
0314     restore_fpcr();         /* Step 13. */
0315     restore_srr0();         /* Step 14. */
0316     restore_event_mask();       /* Step 15. */
0317     restore_tag_mask();     /* Step 16. */
0318                     /* Step 17. done by 'exit'. */
0319     restore_complete();     /* Step 18. */
0320
0321     return 0;
0322 }