platforms/cell/spu_priv1_mmio.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * spu hypervisor abstraction for direct hardware access.
0004  *
0005  *  (C) Copyright IBM Deutschland Entwicklung GmbH 2005
0006  *  Copyright 2006 Sony Corp.
0007  */
0008
0009 #include <linux/interrupt.h>
0010 #include <linux/list.h>
0011 #include <linux/ptrace.h>
0012 #include <linux/wait.h>
0013 #include <linux/mm.h>
0014 #include <linux/io.h>
0015 #include <linux/mutex.h>
0016 #include <linux/device.h>
0017 #include <linux/sched.h>
0018
0019 #include <asm/spu.h>
0020 #include <asm/spu_priv1.h>
0021 #include <asm/firmware.h>
0022
0023 #include "interrupt.h"
0024 #include "spu_priv1_mmio.h"
0025
0026 static void int_mask_and(struct spu *spu, int class, u64 mask)
0027 {
0028     u64 old_mask;
0029
0030     old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
0031     out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
0032 }
0033
0034 static void int_mask_or(struct spu *spu, int class, u64 mask)
0035 {
0036     u64 old_mask;
0037
0038     old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
0039     out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
0040 }
0041
0042 static void int_mask_set(struct spu *spu, int class, u64 mask)
0043 {
0044     out_be64(&spu->priv1->int_mask_RW[class], mask);
0045 }
0046
0047 static u64 int_mask_get(struct spu *spu, int class)
0048 {
0049     return in_be64(&spu->priv1->int_mask_RW[class]);
0050 }
0051
0052 static void int_stat_clear(struct spu *spu, int class, u64 stat)
0053 {
0054     out_be64(&spu->priv1->int_stat_RW[class], stat);
0055 }
0056
0057 static u64 int_stat_get(struct spu *spu, int class)
0058 {
0059     return in_be64(&spu->priv1->int_stat_RW[class]);
0060 }
0061
0062 static void cpu_affinity_set(struct spu *spu, int cpu)
0063 {
0064     u64 target;
0065     u64 route;
0066
0067     if (nr_cpus_node(spu->node)) {
0068         const struct cpumask *spumask = cpumask_of_node(spu->node),
0069             *cpumask = cpumask_of_node(cpu_to_node(cpu));
0070
0071         if (!cpumask_intersects(spumask, cpumask))
0072             return;
0073     }
0074
0075     target = iic_get_target_id(cpu);
0076     route = target << 48 | target << 32 | target << 16;
0077     out_be64(&spu->priv1->int_route_RW, route);
0078 }
0079
0080 static u64 mfc_dar_get(struct spu *spu)
0081 {
0082     return in_be64(&spu->priv1->mfc_dar_RW);
0083 }
0084
0085 static u64 mfc_dsisr_get(struct spu *spu)
0086 {
0087     return in_be64(&spu->priv1->mfc_dsisr_RW);
0088 }
0089
0090 static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
0091 {
0092     out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
0093 }
0094
0095 static void mfc_sdr_setup(struct spu *spu)
0096 {
0097     out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
0098 }
0099
0100 static void mfc_sr1_set(struct spu *spu, u64 sr1)
0101 {
0102     out_be64(&spu->priv1->mfc_sr1_RW, sr1);
0103 }
0104
0105 static u64 mfc_sr1_get(struct spu *spu)
0106 {
0107     return in_be64(&spu->priv1->mfc_sr1_RW);
0108 }
0109
0110 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
0111 {
0112     out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
0113 }
0114
0115 static u64 mfc_tclass_id_get(struct spu *spu)
0116 {
0117     return in_be64(&spu->priv1->mfc_tclass_id_RW);
0118 }
0119
0120 static void tlb_invalidate(struct spu *spu)
0121 {
0122     out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
0123 }
0124
0125 static void resource_allocation_groupID_set(struct spu *spu, u64 id)
0126 {
0127     out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
0128 }
0129
0130 static u64 resource_allocation_groupID_get(struct spu *spu)
0131 {
0132     return in_be64(&spu->priv1->resource_allocation_groupID_RW);
0133 }
0134
0135 static void resource_allocation_enable_set(struct spu *spu, u64 enable)
0136 {
0137     out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
0138 }
0139
0140 static u64 resource_allocation_enable_get(struct spu *spu)
0141 {
0142     return in_be64(&spu->priv1->resource_allocation_enable_RW);
0143 }
0144
0145 const struct spu_priv1_ops spu_priv1_mmio_ops =
0146 {
0147     .int_mask_and = int_mask_and,
0148     .int_mask_or = int_mask_or,
0149     .int_mask_set = int_mask_set,
0150     .int_mask_get = int_mask_get,
0151     .int_stat_clear = int_stat_clear,
0152     .int_stat_get = int_stat_get,
0153     .cpu_affinity_set = cpu_affinity_set,
0154     .mfc_dar_get = mfc_dar_get,
0155     .mfc_dsisr_get = mfc_dsisr_get,
0156     .mfc_dsisr_set = mfc_dsisr_set,
0157     .mfc_sdr_setup = mfc_sdr_setup,
0158     .mfc_sr1_set = mfc_sr1_set,
0159     .mfc_sr1_get = mfc_sr1_get,
0160     .mfc_tclass_id_set = mfc_tclass_id_set,
0161     .mfc_tclass_id_get = mfc_tclass_id_get,
0162     .tlb_invalidate = tlb_invalidate,
0163     .resource_allocation_groupID_set = resource_allocation_groupID_set,
0164     .resource_allocation_groupID_get = resource_allocation_groupID_get,
0165     .resource_allocation_enable_set = resource_allocation_enable_set,
0166     .resource_allocation_enable_get = resource_allocation_enable_get,
0167 };