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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Low-level SPU handling
0004  *
0005  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
0006  *
0007  * Author: Arnd Bergmann <arndb@de.ibm.com>
0008  */
0009 
0010 #undef DEBUG
0011 
0012 #include <linux/interrupt.h>
0013 #include <linux/list.h>
0014 #include <linux/init.h>
0015 #include <linux/ptrace.h>
0016 #include <linux/slab.h>
0017 #include <linux/wait.h>
0018 #include <linux/mm.h>
0019 #include <linux/io.h>
0020 #include <linux/mutex.h>
0021 #include <linux/linux_logo.h>
0022 #include <linux/syscore_ops.h>
0023 #include <asm/spu.h>
0024 #include <asm/spu_priv1.h>
0025 #include <asm/spu_csa.h>
0026 #include <asm/xmon.h>
0027 #include <asm/kexec.h>
0028 
0029 const struct spu_management_ops *spu_management_ops;
0030 EXPORT_SYMBOL_GPL(spu_management_ops);
0031 
0032 const struct spu_priv1_ops *spu_priv1_ops;
0033 EXPORT_SYMBOL_GPL(spu_priv1_ops);
0034 
0035 struct cbe_spu_info cbe_spu_info[MAX_NUMNODES];
0036 EXPORT_SYMBOL_GPL(cbe_spu_info);
0037 
0038 /*
0039  * The spufs fault-handling code needs to call force_sig_fault to raise signals
0040  * on DMA errors. Export it here to avoid general kernel-wide access to this
0041  * function
0042  */
0043 EXPORT_SYMBOL_GPL(force_sig_fault);
0044 
0045 /*
0046  * Protects cbe_spu_info and spu->number.
0047  */
0048 static DEFINE_SPINLOCK(spu_lock);
0049 
0050 /*
0051  * List of all spus in the system.
0052  *
0053  * This list is iterated by callers from irq context and callers that
0054  * want to sleep.  Thus modifications need to be done with both
0055  * spu_full_list_lock and spu_full_list_mutex held, while iterating
0056  * through it requires either of these locks.
0057  *
0058  * In addition spu_full_list_lock protects all assignments to
0059  * spu->mm.
0060  */
0061 static LIST_HEAD(spu_full_list);
0062 static DEFINE_SPINLOCK(spu_full_list_lock);
0063 static DEFINE_MUTEX(spu_full_list_mutex);
0064 
0065 void spu_invalidate_slbs(struct spu *spu)
0066 {
0067     struct spu_priv2 __iomem *priv2 = spu->priv2;
0068     unsigned long flags;
0069 
0070     spin_lock_irqsave(&spu->register_lock, flags);
0071     if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)
0072         out_be64(&priv2->slb_invalidate_all_W, 0UL);
0073     spin_unlock_irqrestore(&spu->register_lock, flags);
0074 }
0075 EXPORT_SYMBOL_GPL(spu_invalidate_slbs);
0076 
0077 /* This is called by the MM core when a segment size is changed, to
0078  * request a flush of all the SPEs using a given mm
0079  */
0080 void spu_flush_all_slbs(struct mm_struct *mm)
0081 {
0082     struct spu *spu;
0083     unsigned long flags;
0084 
0085     spin_lock_irqsave(&spu_full_list_lock, flags);
0086     list_for_each_entry(spu, &spu_full_list, full_list) {
0087         if (spu->mm == mm)
0088             spu_invalidate_slbs(spu);
0089     }
0090     spin_unlock_irqrestore(&spu_full_list_lock, flags);
0091 }
0092 
0093 /* The hack below stinks... try to do something better one of
0094  * these days... Does it even work properly with NR_CPUS == 1 ?
0095  */
0096 static inline void mm_needs_global_tlbie(struct mm_struct *mm)
0097 {
0098     int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1;
0099 
0100     /* Global TLBIE broadcast required with SPEs. */
0101     bitmap_fill(cpumask_bits(mm_cpumask(mm)), nr);
0102 }
0103 
0104 void spu_associate_mm(struct spu *spu, struct mm_struct *mm)
0105 {
0106     unsigned long flags;
0107 
0108     spin_lock_irqsave(&spu_full_list_lock, flags);
0109     spu->mm = mm;
0110     spin_unlock_irqrestore(&spu_full_list_lock, flags);
0111     if (mm)
0112         mm_needs_global_tlbie(mm);
0113 }
0114 EXPORT_SYMBOL_GPL(spu_associate_mm);
0115 
0116 int spu_64k_pages_available(void)
0117 {
0118     return mmu_psize_defs[MMU_PAGE_64K].shift != 0;
0119 }
0120 EXPORT_SYMBOL_GPL(spu_64k_pages_available);
0121 
0122 static void spu_restart_dma(struct spu *spu)
0123 {
0124     struct spu_priv2 __iomem *priv2 = spu->priv2;
0125 
0126     if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
0127         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
0128     else {
0129         set_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags);
0130         mb();
0131     }
0132 }
0133 
0134 static inline void spu_load_slb(struct spu *spu, int slbe, struct copro_slb *slb)
0135 {
0136     struct spu_priv2 __iomem *priv2 = spu->priv2;
0137 
0138     pr_debug("%s: adding SLB[%d] 0x%016llx 0x%016llx\n",
0139             __func__, slbe, slb->vsid, slb->esid);
0140 
0141     out_be64(&priv2->slb_index_W, slbe);
0142     /* set invalid before writing vsid */
0143     out_be64(&priv2->slb_esid_RW, 0);
0144     /* now it's safe to write the vsid */
0145     out_be64(&priv2->slb_vsid_RW, slb->vsid);
0146     /* setting the new esid makes the entry valid again */
0147     out_be64(&priv2->slb_esid_RW, slb->esid);
0148 }
0149 
0150 static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
0151 {
0152     struct copro_slb slb;
0153     int ret;
0154 
0155     ret = copro_calculate_slb(spu->mm, ea, &slb);
0156     if (ret)
0157         return ret;
0158 
0159     spu_load_slb(spu, spu->slb_replace, &slb);
0160 
0161     spu->slb_replace++;
0162     if (spu->slb_replace >= 8)
0163         spu->slb_replace = 0;
0164 
0165     spu_restart_dma(spu);
0166     spu->stats.slb_flt++;
0167     return 0;
0168 }
0169 
0170 extern int hash_page(unsigned long ea, unsigned long access,
0171              unsigned long trap, unsigned long dsisr); //XXX
0172 static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
0173 {
0174     int ret;
0175 
0176     pr_debug("%s, %llx, %lx\n", __func__, dsisr, ea);
0177 
0178     /*
0179      * Handle kernel space hash faults immediately. User hash
0180      * faults need to be deferred to process context.
0181      */
0182     if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) &&
0183         (get_region_id(ea) != USER_REGION_ID)) {
0184 
0185         spin_unlock(&spu->register_lock);
0186         ret = hash_page(ea,
0187                 _PAGE_PRESENT | _PAGE_READ | _PAGE_PRIVILEGED,
0188                 0x300, dsisr);
0189         spin_lock(&spu->register_lock);
0190 
0191         if (!ret) {
0192             spu_restart_dma(spu);
0193             return 0;
0194         }
0195     }
0196 
0197     spu->class_1_dar = ea;
0198     spu->class_1_dsisr = dsisr;
0199 
0200     spu->stop_callback(spu, 1);
0201 
0202     spu->class_1_dar = 0;
0203     spu->class_1_dsisr = 0;
0204 
0205     return 0;
0206 }
0207 
0208 static void __spu_kernel_slb(void *addr, struct copro_slb *slb)
0209 {
0210     unsigned long ea = (unsigned long)addr;
0211     u64 llp;
0212 
0213     if (get_region_id(ea) == LINEAR_MAP_REGION_ID)
0214         llp = mmu_psize_defs[mmu_linear_psize].sllp;
0215     else
0216         llp = mmu_psize_defs[mmu_virtual_psize].sllp;
0217 
0218     slb->vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) << SLB_VSID_SHIFT) |
0219         SLB_VSID_KERNEL | llp;
0220     slb->esid = (ea & ESID_MASK) | SLB_ESID_V;
0221 }
0222 
0223 /**
0224  * Given an array of @nr_slbs SLB entries, @slbs, return non-zero if the
0225  * address @new_addr is present.
0226  */
0227 static inline int __slb_present(struct copro_slb *slbs, int nr_slbs,
0228         void *new_addr)
0229 {
0230     unsigned long ea = (unsigned long)new_addr;
0231     int i;
0232 
0233     for (i = 0; i < nr_slbs; i++)
0234         if (!((slbs[i].esid ^ ea) & ESID_MASK))
0235             return 1;
0236 
0237     return 0;
0238 }
0239 
0240 /**
0241  * Setup the SPU kernel SLBs, in preparation for a context save/restore. We
0242  * need to map both the context save area, and the save/restore code.
0243  *
0244  * Because the lscsa and code may cross segment boundaries, we check to see
0245  * if mappings are required for the start and end of each range. We currently
0246  * assume that the mappings are smaller that one segment - if not, something
0247  * is seriously wrong.
0248  */
0249 void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
0250         void *code, int code_size)
0251 {
0252     struct copro_slb slbs[4];
0253     int i, nr_slbs = 0;
0254     /* start and end addresses of both mappings */
0255     void *addrs[] = {
0256         lscsa, (void *)lscsa + sizeof(*lscsa) - 1,
0257         code, code + code_size - 1
0258     };
0259 
0260     /* check the set of addresses, and create a new entry in the slbs array
0261      * if there isn't already a SLB for that address */
0262     for (i = 0; i < ARRAY_SIZE(addrs); i++) {
0263         if (__slb_present(slbs, nr_slbs, addrs[i]))
0264             continue;
0265 
0266         __spu_kernel_slb(addrs[i], &slbs[nr_slbs]);
0267         nr_slbs++;
0268     }
0269 
0270     spin_lock_irq(&spu->register_lock);
0271     /* Add the set of SLBs */
0272     for (i = 0; i < nr_slbs; i++)
0273         spu_load_slb(spu, i, &slbs[i]);
0274     spin_unlock_irq(&spu->register_lock);
0275 }
0276 EXPORT_SYMBOL_GPL(spu_setup_kernel_slbs);
0277 
0278 static irqreturn_t
0279 spu_irq_class_0(int irq, void *data)
0280 {
0281     struct spu *spu;
0282     unsigned long stat, mask;
0283 
0284     spu = data;
0285 
0286     spin_lock(&spu->register_lock);
0287     mask = spu_int_mask_get(spu, 0);
0288     stat = spu_int_stat_get(spu, 0) & mask;
0289 
0290     spu->class_0_pending |= stat;
0291     spu->class_0_dar = spu_mfc_dar_get(spu);
0292     spu->stop_callback(spu, 0);
0293     spu->class_0_pending = 0;
0294     spu->class_0_dar = 0;
0295 
0296     spu_int_stat_clear(spu, 0, stat);
0297     spin_unlock(&spu->register_lock);
0298 
0299     return IRQ_HANDLED;
0300 }
0301 
0302 static irqreturn_t
0303 spu_irq_class_1(int irq, void *data)
0304 {
0305     struct spu *spu;
0306     unsigned long stat, mask, dar, dsisr;
0307 
0308     spu = data;
0309 
0310     /* atomically read & clear class1 status. */
0311     spin_lock(&spu->register_lock);
0312     mask  = spu_int_mask_get(spu, 1);
0313     stat  = spu_int_stat_get(spu, 1) & mask;
0314     dar   = spu_mfc_dar_get(spu);
0315     dsisr = spu_mfc_dsisr_get(spu);
0316     if (stat & CLASS1_STORAGE_FAULT_INTR)
0317         spu_mfc_dsisr_set(spu, 0ul);
0318     spu_int_stat_clear(spu, 1, stat);
0319 
0320     pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat,
0321             dar, dsisr);
0322 
0323     if (stat & CLASS1_SEGMENT_FAULT_INTR)
0324         __spu_trap_data_seg(spu, dar);
0325 
0326     if (stat & CLASS1_STORAGE_FAULT_INTR)
0327         __spu_trap_data_map(spu, dar, dsisr);
0328 
0329     if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR)
0330         ;
0331 
0332     if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR)
0333         ;
0334 
0335     spu->class_1_dsisr = 0;
0336     spu->class_1_dar = 0;
0337 
0338     spin_unlock(&spu->register_lock);
0339 
0340     return stat ? IRQ_HANDLED : IRQ_NONE;
0341 }
0342 
0343 static irqreturn_t
0344 spu_irq_class_2(int irq, void *data)
0345 {
0346     struct spu *spu;
0347     unsigned long stat;
0348     unsigned long mask;
0349     const int mailbox_intrs =
0350         CLASS2_MAILBOX_THRESHOLD_INTR | CLASS2_MAILBOX_INTR;
0351 
0352     spu = data;
0353     spin_lock(&spu->register_lock);
0354     stat = spu_int_stat_get(spu, 2);
0355     mask = spu_int_mask_get(spu, 2);
0356     /* ignore interrupts we're not waiting for */
0357     stat &= mask;
0358     /* mailbox interrupts are level triggered. mask them now before
0359      * acknowledging */
0360     if (stat & mailbox_intrs)
0361         spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs));
0362     /* acknowledge all interrupts before the callbacks */
0363     spu_int_stat_clear(spu, 2, stat);
0364 
0365     pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
0366 
0367     if (stat & CLASS2_MAILBOX_INTR)
0368         spu->ibox_callback(spu);
0369 
0370     if (stat & CLASS2_SPU_STOP_INTR)
0371         spu->stop_callback(spu, 2);
0372 
0373     if (stat & CLASS2_SPU_HALT_INTR)
0374         spu->stop_callback(spu, 2);
0375 
0376     if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR)
0377         spu->mfc_callback(spu);
0378 
0379     if (stat & CLASS2_MAILBOX_THRESHOLD_INTR)
0380         spu->wbox_callback(spu);
0381 
0382     spu->stats.class2_intr++;
0383 
0384     spin_unlock(&spu->register_lock);
0385 
0386     return stat ? IRQ_HANDLED : IRQ_NONE;
0387 }
0388 
0389 static int __init spu_request_irqs(struct spu *spu)
0390 {
0391     int ret = 0;
0392 
0393     if (spu->irqs[0]) {
0394         snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0",
0395              spu->number);
0396         ret = request_irq(spu->irqs[0], spu_irq_class_0,
0397                   0, spu->irq_c0, spu);
0398         if (ret)
0399             goto bail0;
0400     }
0401     if (spu->irqs[1]) {
0402         snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1",
0403              spu->number);
0404         ret = request_irq(spu->irqs[1], spu_irq_class_1,
0405                   0, spu->irq_c1, spu);
0406         if (ret)
0407             goto bail1;
0408     }
0409     if (spu->irqs[2]) {
0410         snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2",
0411              spu->number);
0412         ret = request_irq(spu->irqs[2], spu_irq_class_2,
0413                   0, spu->irq_c2, spu);
0414         if (ret)
0415             goto bail2;
0416     }
0417     return 0;
0418 
0419 bail2:
0420     if (spu->irqs[1])
0421         free_irq(spu->irqs[1], spu);
0422 bail1:
0423     if (spu->irqs[0])
0424         free_irq(spu->irqs[0], spu);
0425 bail0:
0426     return ret;
0427 }
0428 
0429 static void spu_free_irqs(struct spu *spu)
0430 {
0431     if (spu->irqs[0])
0432         free_irq(spu->irqs[0], spu);
0433     if (spu->irqs[1])
0434         free_irq(spu->irqs[1], spu);
0435     if (spu->irqs[2])
0436         free_irq(spu->irqs[2], spu);
0437 }
0438 
0439 void spu_init_channels(struct spu *spu)
0440 {
0441     static const struct {
0442          unsigned channel;
0443          unsigned count;
0444     } zero_list[] = {
0445         { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
0446         { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
0447     }, count_list[] = {
0448         { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
0449         { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
0450         { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
0451     };
0452     struct spu_priv2 __iomem *priv2;
0453     int i;
0454 
0455     priv2 = spu->priv2;
0456 
0457     /* initialize all channel data to zero */
0458     for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
0459         int count;
0460 
0461         out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
0462         for (count = 0; count < zero_list[i].count; count++)
0463             out_be64(&priv2->spu_chnldata_RW, 0);
0464     }
0465 
0466     /* initialize channel counts to meaningful values */
0467     for (i = 0; i < ARRAY_SIZE(count_list); i++) {
0468         out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
0469         out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
0470     }
0471 }
0472 EXPORT_SYMBOL_GPL(spu_init_channels);
0473 
0474 static struct bus_type spu_subsys = {
0475     .name = "spu",
0476     .dev_name = "spu",
0477 };
0478 
0479 int spu_add_dev_attr(struct device_attribute *attr)
0480 {
0481     struct spu *spu;
0482 
0483     mutex_lock(&spu_full_list_mutex);
0484     list_for_each_entry(spu, &spu_full_list, full_list)
0485         device_create_file(&spu->dev, attr);
0486     mutex_unlock(&spu_full_list_mutex);
0487 
0488     return 0;
0489 }
0490 EXPORT_SYMBOL_GPL(spu_add_dev_attr);
0491 
0492 int spu_add_dev_attr_group(const struct attribute_group *attrs)
0493 {
0494     struct spu *spu;
0495     int rc = 0;
0496 
0497     mutex_lock(&spu_full_list_mutex);
0498     list_for_each_entry(spu, &spu_full_list, full_list) {
0499         rc = sysfs_create_group(&spu->dev.kobj, attrs);
0500 
0501         /* we're in trouble here, but try unwinding anyway */
0502         if (rc) {
0503             printk(KERN_ERR "%s: can't create sysfs group '%s'\n",
0504                     __func__, attrs->name);
0505 
0506             list_for_each_entry_continue_reverse(spu,
0507                     &spu_full_list, full_list)
0508                 sysfs_remove_group(&spu->dev.kobj, attrs);
0509             break;
0510         }
0511     }
0512 
0513     mutex_unlock(&spu_full_list_mutex);
0514 
0515     return rc;
0516 }
0517 EXPORT_SYMBOL_GPL(spu_add_dev_attr_group);
0518 
0519 
0520 void spu_remove_dev_attr(struct device_attribute *attr)
0521 {
0522     struct spu *spu;
0523 
0524     mutex_lock(&spu_full_list_mutex);
0525     list_for_each_entry(spu, &spu_full_list, full_list)
0526         device_remove_file(&spu->dev, attr);
0527     mutex_unlock(&spu_full_list_mutex);
0528 }
0529 EXPORT_SYMBOL_GPL(spu_remove_dev_attr);
0530 
0531 void spu_remove_dev_attr_group(const struct attribute_group *attrs)
0532 {
0533     struct spu *spu;
0534 
0535     mutex_lock(&spu_full_list_mutex);
0536     list_for_each_entry(spu, &spu_full_list, full_list)
0537         sysfs_remove_group(&spu->dev.kobj, attrs);
0538     mutex_unlock(&spu_full_list_mutex);
0539 }
0540 EXPORT_SYMBOL_GPL(spu_remove_dev_attr_group);
0541 
0542 static int __init spu_create_dev(struct spu *spu)
0543 {
0544     int ret;
0545 
0546     spu->dev.id = spu->number;
0547     spu->dev.bus = &spu_subsys;
0548     ret = device_register(&spu->dev);
0549     if (ret) {
0550         printk(KERN_ERR "Can't register SPU %d with sysfs\n",
0551                 spu->number);
0552         return ret;
0553     }
0554 
0555     sysfs_add_device_to_node(&spu->dev, spu->node);
0556 
0557     return 0;
0558 }
0559 
0560 static int __init create_spu(void *data)
0561 {
0562     struct spu *spu;
0563     int ret;
0564     static int number;
0565     unsigned long flags;
0566 
0567     ret = -ENOMEM;
0568     spu = kzalloc(sizeof (*spu), GFP_KERNEL);
0569     if (!spu)
0570         goto out;
0571 
0572     spu->alloc_state = SPU_FREE;
0573 
0574     spin_lock_init(&spu->register_lock);
0575     spin_lock(&spu_lock);
0576     spu->number = number++;
0577     spin_unlock(&spu_lock);
0578 
0579     ret = spu_create_spu(spu, data);
0580 
0581     if (ret)
0582         goto out_free;
0583 
0584     spu_mfc_sdr_setup(spu);
0585     spu_mfc_sr1_set(spu, 0x33);
0586     ret = spu_request_irqs(spu);
0587     if (ret)
0588         goto out_destroy;
0589 
0590     ret = spu_create_dev(spu);
0591     if (ret)
0592         goto out_free_irqs;
0593 
0594     mutex_lock(&cbe_spu_info[spu->node].list_mutex);
0595     list_add(&spu->cbe_list, &cbe_spu_info[spu->node].spus);
0596     cbe_spu_info[spu->node].n_spus++;
0597     mutex_unlock(&cbe_spu_info[spu->node].list_mutex);
0598 
0599     mutex_lock(&spu_full_list_mutex);
0600     spin_lock_irqsave(&spu_full_list_lock, flags);
0601     list_add(&spu->full_list, &spu_full_list);
0602     spin_unlock_irqrestore(&spu_full_list_lock, flags);
0603     mutex_unlock(&spu_full_list_mutex);
0604 
0605     spu->stats.util_state = SPU_UTIL_IDLE_LOADED;
0606     spu->stats.tstamp = ktime_get_ns();
0607 
0608     INIT_LIST_HEAD(&spu->aff_list);
0609 
0610     goto out;
0611 
0612 out_free_irqs:
0613     spu_free_irqs(spu);
0614 out_destroy:
0615     spu_destroy_spu(spu);
0616 out_free:
0617     kfree(spu);
0618 out:
0619     return ret;
0620 }
0621 
0622 static const char *spu_state_names[] = {
0623     "user", "system", "iowait", "idle"
0624 };
0625 
0626 static unsigned long long spu_acct_time(struct spu *spu,
0627         enum spu_utilization_state state)
0628 {
0629     unsigned long long time = spu->stats.times[state];
0630 
0631     /*
0632      * If the spu is idle or the context is stopped, utilization
0633      * statistics are not updated.  Apply the time delta from the
0634      * last recorded state of the spu.
0635      */
0636     if (spu->stats.util_state == state)
0637         time += ktime_get_ns() - spu->stats.tstamp;
0638 
0639     return time / NSEC_PER_MSEC;
0640 }
0641 
0642 
0643 static ssize_t spu_stat_show(struct device *dev,
0644                 struct device_attribute *attr, char *buf)
0645 {
0646     struct spu *spu = container_of(dev, struct spu, dev);
0647 
0648     return sprintf(buf, "%s %llu %llu %llu %llu "
0649               "%llu %llu %llu %llu %llu %llu %llu %llu\n",
0650         spu_state_names[spu->stats.util_state],
0651         spu_acct_time(spu, SPU_UTIL_USER),
0652         spu_acct_time(spu, SPU_UTIL_SYSTEM),
0653         spu_acct_time(spu, SPU_UTIL_IOWAIT),
0654         spu_acct_time(spu, SPU_UTIL_IDLE_LOADED),
0655         spu->stats.vol_ctx_switch,
0656         spu->stats.invol_ctx_switch,
0657         spu->stats.slb_flt,
0658         spu->stats.hash_flt,
0659         spu->stats.min_flt,
0660         spu->stats.maj_flt,
0661         spu->stats.class2_intr,
0662         spu->stats.libassist);
0663 }
0664 
0665 static DEVICE_ATTR(stat, 0444, spu_stat_show, NULL);
0666 
0667 #ifdef CONFIG_KEXEC_CORE
0668 
0669 struct crash_spu_info {
0670     struct spu *spu;
0671     u32 saved_spu_runcntl_RW;
0672     u32 saved_spu_status_R;
0673     u32 saved_spu_npc_RW;
0674     u64 saved_mfc_sr1_RW;
0675     u64 saved_mfc_dar;
0676     u64 saved_mfc_dsisr;
0677 };
0678 
0679 #define CRASH_NUM_SPUS  16  /* Enough for current hardware */
0680 static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS];
0681 
0682 static void crash_kexec_stop_spus(void)
0683 {
0684     struct spu *spu;
0685     int i;
0686     u64 tmp;
0687 
0688     for (i = 0; i < CRASH_NUM_SPUS; i++) {
0689         if (!crash_spu_info[i].spu)
0690             continue;
0691 
0692         spu = crash_spu_info[i].spu;
0693 
0694         crash_spu_info[i].saved_spu_runcntl_RW =
0695             in_be32(&spu->problem->spu_runcntl_RW);
0696         crash_spu_info[i].saved_spu_status_R =
0697             in_be32(&spu->problem->spu_status_R);
0698         crash_spu_info[i].saved_spu_npc_RW =
0699             in_be32(&spu->problem->spu_npc_RW);
0700 
0701         crash_spu_info[i].saved_mfc_dar    = spu_mfc_dar_get(spu);
0702         crash_spu_info[i].saved_mfc_dsisr  = spu_mfc_dsisr_get(spu);
0703         tmp = spu_mfc_sr1_get(spu);
0704         crash_spu_info[i].saved_mfc_sr1_RW = tmp;
0705 
0706         tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
0707         spu_mfc_sr1_set(spu, tmp);
0708 
0709         __delay(200);
0710     }
0711 }
0712 
0713 static void __init crash_register_spus(struct list_head *list)
0714 {
0715     struct spu *spu;
0716     int ret;
0717 
0718     list_for_each_entry(spu, list, full_list) {
0719         if (WARN_ON(spu->number >= CRASH_NUM_SPUS))
0720             continue;
0721 
0722         crash_spu_info[spu->number].spu = spu;
0723     }
0724 
0725     ret = crash_shutdown_register(&crash_kexec_stop_spus);
0726     if (ret)
0727         printk(KERN_ERR "Could not register SPU crash handler");
0728 }
0729 
0730 #else
0731 static inline void crash_register_spus(struct list_head *list)
0732 {
0733 }
0734 #endif
0735 
0736 static void spu_shutdown(void)
0737 {
0738     struct spu *spu;
0739 
0740     mutex_lock(&spu_full_list_mutex);
0741     list_for_each_entry(spu, &spu_full_list, full_list) {
0742         spu_free_irqs(spu);
0743         spu_destroy_spu(spu);
0744     }
0745     mutex_unlock(&spu_full_list_mutex);
0746 }
0747 
0748 static struct syscore_ops spu_syscore_ops = {
0749     .shutdown = spu_shutdown,
0750 };
0751 
0752 static int __init init_spu_base(void)
0753 {
0754     int i, ret = 0;
0755 
0756     for (i = 0; i < MAX_NUMNODES; i++) {
0757         mutex_init(&cbe_spu_info[i].list_mutex);
0758         INIT_LIST_HEAD(&cbe_spu_info[i].spus);
0759     }
0760 
0761     if (!spu_management_ops)
0762         goto out;
0763 
0764     /* create system subsystem for spus */
0765     ret = subsys_system_register(&spu_subsys, NULL);
0766     if (ret)
0767         goto out;
0768 
0769     ret = spu_enumerate_spus(create_spu);
0770 
0771     if (ret < 0) {
0772         printk(KERN_WARNING "%s: Error initializing spus\n",
0773             __func__);
0774         goto out_unregister_subsys;
0775     }
0776 
0777     if (ret > 0)
0778         fb_append_extra_logo(&logo_spe_clut224, ret);
0779 
0780     mutex_lock(&spu_full_list_mutex);
0781     xmon_register_spus(&spu_full_list);
0782     crash_register_spus(&spu_full_list);
0783     mutex_unlock(&spu_full_list_mutex);
0784     spu_add_dev_attr(&dev_attr_stat);
0785     register_syscore_ops(&spu_syscore_ops);
0786 
0787     spu_init_affinity();
0788 
0789     return 0;
0790 
0791  out_unregister_subsys:
0792     bus_unregister(&spu_subsys);
0793  out:
0794     return ret;
0795 }
0796 device_initcall(init_spu_base);
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