platforms/cell/setup.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  linux/arch/powerpc/platforms/cell/cell_setup.c
0004  *
0005  *  Copyright (C) 1995  Linus Torvalds
0006  *  Adapted from 'alpha' version by Gary Thomas
0007  *  Modified by Cort Dougan (cort@cs.nmt.edu)
0008  *  Modified by PPC64 Team, IBM Corp
0009  *  Modified by Cell Team, IBM Deutschland Entwicklung GmbH
0010  */
0011 #undef DEBUG
0012
0013 #include <linux/sched.h>
0014 #include <linux/kernel.h>
0015 #include <linux/mm.h>
0016 #include <linux/stddef.h>
0017 #include <linux/export.h>
0018 #include <linux/unistd.h>
0019 #include <linux/user.h>
0020 #include <linux/reboot.h>
0021 #include <linux/init.h>
0022 #include <linux/delay.h>
0023 #include <linux/irq.h>
0024 #include <linux/seq_file.h>
0025 #include <linux/root_dev.h>
0026 #include <linux/console.h>
0027 #include <linux/mutex.h>
0028 #include <linux/memory_hotplug.h>
0029 #include <linux/of_platform.h>
0030
0031 #include <asm/mmu.h>
0032 #include <asm/processor.h>
0033 #include <asm/io.h>
0034 #include <asm/rtas.h>
0035 #include <asm/pci-bridge.h>
0036 #include <asm/iommu.h>
0037 #include <asm/dma.h>
0038 #include <asm/machdep.h>
0039 #include <asm/time.h>
0040 #include <asm/nvram.h>
0041 #include <asm/cputable.h>
0042 #include <asm/ppc-pci.h>
0043 #include <asm/irq.h>
0044 #include <asm/spu.h>
0045 #include <asm/spu_priv1.h>
0046 #include <asm/udbg.h>
0047 #include <asm/mpic.h>
0048 #include <asm/cell-regs.h>
0049 #include <asm/io-workarounds.h>
0050
0051 #include "cell.h"
0052 #include "interrupt.h"
0053 #include "pervasive.h"
0054 #include "ras.h"
0055
0056 #ifdef DEBUG
0057 #define DBG(fmt...) udbg_printf(fmt)
0058 #else
0059 #define DBG(fmt...)
0060 #endif
0061
0062 static void cell_show_cpuinfo(struct seq_file *m)
0063 {
0064     struct device_node *root;
0065     const char *model = "";
0066
0067     root = of_find_node_by_path("/");
0068     if (root)
0069         model = of_get_property(root, "model", NULL);
0070     seq_printf(m, "machine\t\t: CHRP %s\n", model);
0071     of_node_put(root);
0072 }
0073
0074 static void cell_progress(char *s, unsigned short hex)
0075 {
0076     printk("*** %04x : %s\n", hex, s ? s : "");
0077 }
0078
0079 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
0080 {
0081     struct pci_controller *hose;
0082     const char *s;
0083     int i;
0084
0085     if (!machine_is(cell))
0086         return;
0087
0088     /* We're searching for a direct child of the PHB */
0089     if (dev->bus->self != NULL || dev->devfn != 0)
0090         return;
0091
0092     hose = pci_bus_to_host(dev->bus);
0093     if (hose == NULL)
0094         return;
0095
0096     /* Only on PCIE */
0097     if (!of_device_is_compatible(hose->dn, "pciex"))
0098         return;
0099
0100     /* And only on axon */
0101     s = of_get_property(hose->dn, "model", NULL);
0102     if (!s || strcmp(s, "Axon") != 0)
0103         return;
0104
0105     for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
0106         dev->resource[i].start = dev->resource[i].end = 0;
0107         dev->resource[i].flags = 0;
0108     }
0109
0110     printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
0111            pci_name(dev));
0112 }
0113 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
0114
0115 static int cell_setup_phb(struct pci_controller *phb)
0116 {
0117     const char *model;
0118     struct device_node *np;
0119
0120     int rc = rtas_setup_phb(phb);
0121     if (rc)
0122         return rc;
0123
0124     phb->controller_ops = cell_pci_controller_ops;
0125
0126     np = phb->dn;
0127     model = of_get_property(np, "model", NULL);
0128     if (model == NULL || !of_node_name_eq(np, "pci"))
0129         return 0;
0130
0131     /* Setup workarounds for spider */
0132     if (strcmp(model, "Spider"))
0133         return 0;
0134
0135     iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
0136                   (void *)SPIDER_PCI_REG_BASE);
0137     return 0;
0138 }
0139
0140 static const struct of_device_id cell_bus_ids[] __initconst = {
0141     { .type = "soc", },
0142     { .compatible = "soc", },
0143     { .type = "spider", },
0144     { .type = "axon", },
0145     { .type = "plb5", },
0146     { .type = "plb4", },
0147     { .type = "opb", },
0148     { .type = "ebc", },
0149     {},
0150 };
0151
0152 static int __init cell_publish_devices(void)
0153 {
0154     struct device_node *root = of_find_node_by_path("/");
0155     struct device_node *np;
0156     int node;
0157
0158     /* Publish OF platform devices for southbridge IOs */
0159     of_platform_bus_probe(NULL, cell_bus_ids, NULL);
0160
0161     /* On spider based blades, we need to manually create the OF
0162      * platform devices for the PCI host bridges
0163      */
0164     for_each_child_of_node(root, np) {
0165         if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "pciex"))
0166             continue;
0167         of_platform_device_create(np, NULL, NULL);
0168     }
0169
0170     /* There is no device for the MIC memory controller, thus we create
0171      * a platform device for it to attach the EDAC driver to.
0172      */
0173     for_each_online_node(node) {
0174         if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
0175             continue;
0176         platform_device_register_simple("cbe-mic", node, NULL, 0);
0177     }
0178
0179     return 0;
0180 }
0181 machine_subsys_initcall(cell, cell_publish_devices);
0182
0183 static void __init mpic_init_IRQ(void)
0184 {
0185     struct device_node *dn;
0186     struct mpic *mpic;
0187
0188     for_each_node_by_name(dn, "interrupt-controller") {
0189         if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
0190             continue;
0191
0192         /* The MPIC driver will get everything it needs from the
0193          * device-tree, just pass 0 to all arguments
0194          */
0195         mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET,
0196                 0, 0, " MPIC     ");
0197         if (mpic == NULL)
0198             continue;
0199         mpic_init(mpic);
0200     }
0201 }
0202
0203
0204 static void __init cell_init_irq(void)
0205 {
0206     iic_init_IRQ();
0207     spider_init_IRQ();
0208     mpic_init_IRQ();
0209 }
0210
0211 static void __init cell_set_dabrx(void)
0212 {
0213     mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
0214 }
0215
0216 static void __init cell_setup_arch(void)
0217 {
0218 #ifdef CONFIG_SPU_BASE
0219     spu_priv1_ops = &spu_priv1_mmio_ops;
0220     spu_management_ops = &spu_management_of_ops;
0221 #endif
0222
0223     cbe_regs_init();
0224
0225     cell_set_dabrx();
0226
0227 #ifdef CONFIG_CBE_RAS
0228     cbe_ras_init();
0229 #endif
0230
0231 #ifdef CONFIG_SMP
0232     smp_init_cell();
0233 #endif
0234     /* init to some ~sane value until calibrate_delay() runs */
0235     loops_per_jiffy = 50000000;
0236
0237     /* Find and initialize PCI host bridges */
0238     init_pci_config_tokens();
0239
0240     cbe_pervasive_init();
0241
0242     mmio_nvram_init();
0243 }
0244
0245 static int __init cell_probe(void)
0246 {
0247     if (!of_machine_is_compatible("IBM,CBEA") &&
0248         !of_machine_is_compatible("IBM,CPBW-1.0"))
0249         return 0;
0250
0251     pm_power_off = rtas_power_off;
0252
0253     return 1;
0254 }
0255
0256 define_machine(cell) {
0257     .name           = "Cell",
0258     .probe          = cell_probe,
0259     .setup_arch     = cell_setup_arch,
0260     .show_cpuinfo       = cell_show_cpuinfo,
0261     .restart        = rtas_restart,
0262     .halt           = rtas_halt,
0263     .get_boot_time      = rtas_get_boot_time,
0264     .get_rtc_time       = rtas_get_rtc_time,
0265     .set_rtc_time       = rtas_set_rtc_time,
0266     .calibrate_decr     = generic_calibrate_decr,
0267     .progress       = cell_progress,
0268     .init_IRQ           = cell_init_irq,
0269     .pci_setup_phb      = cell_setup_phb,
0270 };
0271
0272 struct pci_controller_ops cell_pci_controller_ops;