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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * IOMMU implementation for Cell Broadband Processor Architecture
0004  *
0005  * (C) Copyright IBM Corporation 2006-2008
0006  *
0007  * Author: Jeremy Kerr <jk@ozlabs.org>
0008  */
0009 
0010 #undef DEBUG
0011 
0012 #include <linux/kernel.h>
0013 #include <linux/init.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/irqdomain.h>
0016 #include <linux/notifier.h>
0017 #include <linux/of.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/slab.h>
0021 #include <linux/memblock.h>
0022 
0023 #include <asm/prom.h>
0024 #include <asm/iommu.h>
0025 #include <asm/machdep.h>
0026 #include <asm/pci-bridge.h>
0027 #include <asm/udbg.h>
0028 #include <asm/firmware.h>
0029 #include <asm/cell-regs.h>
0030 
0031 #include "cell.h"
0032 #include "interrupt.h"
0033 
0034 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
0035  * instead of leaving them mapped to some dummy page. This can be
0036  * enabled once the appropriate workarounds for spider bugs have
0037  * been enabled
0038  */
0039 #define CELL_IOMMU_REAL_UNMAP
0040 
0041 /* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of
0042  * IO PTEs based on the transfer direction. That can be enabled
0043  * once spider-net has been fixed to pass the correct direction
0044  * to the DMA mapping functions
0045  */
0046 #define CELL_IOMMU_STRICT_PROTECTION
0047 
0048 
0049 #define NR_IOMMUS           2
0050 
0051 /* IOC mmap registers */
0052 #define IOC_Reg_Size            0x2000
0053 
0054 #define IOC_IOPT_CacheInvd      0x908
0055 #define IOC_IOPT_CacheInvd_NE_Mask  0xffe0000000000000ul
0056 #define IOC_IOPT_CacheInvd_IOPTE_Mask   0x000003fffffffff8ul
0057 #define IOC_IOPT_CacheInvd_Busy     0x0000000000000001ul
0058 
0059 #define IOC_IOST_Origin         0x918
0060 #define IOC_IOST_Origin_E       0x8000000000000000ul
0061 #define IOC_IOST_Origin_HW      0x0000000000000800ul
0062 #define IOC_IOST_Origin_HL      0x0000000000000400ul
0063 
0064 #define IOC_IO_ExcpStat         0x920
0065 #define IOC_IO_ExcpStat_V       0x8000000000000000ul
0066 #define IOC_IO_ExcpStat_SPF_Mask    0x6000000000000000ul
0067 #define IOC_IO_ExcpStat_SPF_S       0x6000000000000000ul
0068 #define IOC_IO_ExcpStat_SPF_P       0x2000000000000000ul
0069 #define IOC_IO_ExcpStat_ADDR_Mask   0x00000007fffff000ul
0070 #define IOC_IO_ExcpStat_RW_Mask     0x0000000000000800ul
0071 #define IOC_IO_ExcpStat_IOID_Mask   0x00000000000007fful
0072 
0073 #define IOC_IO_ExcpMask         0x928
0074 #define IOC_IO_ExcpMask_SFE     0x4000000000000000ul
0075 #define IOC_IO_ExcpMask_PFE     0x2000000000000000ul
0076 
0077 #define IOC_IOCmd_Offset        0x1000
0078 
0079 #define IOC_IOCmd_Cfg           0xc00
0080 #define IOC_IOCmd_Cfg_TE        0x0000800000000000ul
0081 
0082 
0083 /* Segment table entries */
0084 #define IOSTE_V         0x8000000000000000ul /* valid */
0085 #define IOSTE_H         0x4000000000000000ul /* cache hint */
0086 #define IOSTE_PT_Base_RPN_Mask  0x3ffffffffffff000ul /* base RPN of IOPT */
0087 #define IOSTE_NPPT_Mask     0x0000000000000fe0ul /* no. pages in IOPT */
0088 #define IOSTE_PS_Mask       0x0000000000000007ul /* page size */
0089 #define IOSTE_PS_4K     0x0000000000000001ul /*   - 4kB  */
0090 #define IOSTE_PS_64K        0x0000000000000003ul /*   - 64kB */
0091 #define IOSTE_PS_1M     0x0000000000000005ul /*   - 1MB  */
0092 #define IOSTE_PS_16M        0x0000000000000007ul /*   - 16MB */
0093 
0094 
0095 /* IOMMU sizing */
0096 #define IO_SEGMENT_SHIFT    28
0097 #define IO_PAGENO_BITS(shift)   (IO_SEGMENT_SHIFT - (shift))
0098 
0099 /* The high bit needs to be set on every DMA address */
0100 #define SPIDER_DMA_OFFSET   0x80000000ul
0101 
0102 struct iommu_window {
0103     struct list_head list;
0104     struct cbe_iommu *iommu;
0105     unsigned long offset;
0106     unsigned long size;
0107     unsigned int ioid;
0108     struct iommu_table table;
0109 };
0110 
0111 #define NAMESIZE 8
0112 struct cbe_iommu {
0113     int nid;
0114     char name[NAMESIZE];
0115     void __iomem *xlate_regs;
0116     void __iomem *cmd_regs;
0117     unsigned long *stab;
0118     unsigned long *ptab;
0119     void *pad_page;
0120     struct list_head windows;
0121 };
0122 
0123 /* Static array of iommus, one per node
0124  *   each contains a list of windows, keyed from dma_window property
0125  *   - on bus setup, look for a matching window, or create one
0126  *   - on dev setup, assign iommu_table ptr
0127  */
0128 static struct cbe_iommu iommus[NR_IOMMUS];
0129 static int cbe_nr_iommus;
0130 
0131 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte,
0132         long n_ptes)
0133 {
0134     u64 __iomem *reg;
0135     u64 val;
0136     long n;
0137 
0138     reg = iommu->xlate_regs + IOC_IOPT_CacheInvd;
0139 
0140     while (n_ptes > 0) {
0141         /* we can invalidate up to 1 << 11 PTEs at once */
0142         n = min(n_ptes, 1l << 11);
0143         val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask)
0144             | (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask)
0145                 | IOC_IOPT_CacheInvd_Busy;
0146 
0147         out_be64(reg, val);
0148         while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy)
0149             ;
0150 
0151         n_ptes -= n;
0152         pte += n;
0153     }
0154 }
0155 
0156 static int tce_build_cell(struct iommu_table *tbl, long index, long npages,
0157         unsigned long uaddr, enum dma_data_direction direction,
0158         unsigned long attrs)
0159 {
0160     int i;
0161     unsigned long *io_pte, base_pte;
0162     struct iommu_window *window =
0163         container_of(tbl, struct iommu_window, table);
0164 
0165     /* implementing proper protection causes problems with the spidernet
0166      * driver - check mapping directions later, but allow read & write by
0167      * default for now.*/
0168 #ifdef CELL_IOMMU_STRICT_PROTECTION
0169     /* to avoid referencing a global, we use a trick here to setup the
0170      * protection bit. "prot" is setup to be 3 fields of 4 bits appended
0171      * together for each of the 3 supported direction values. It is then
0172      * shifted left so that the fields matching the desired direction
0173      * lands on the appropriate bits, and other bits are masked out.
0174      */
0175     const unsigned long prot = 0xc48;
0176     base_pte =
0177         ((prot << (52 + 4 * direction)) &
0178          (CBE_IOPTE_PP_W | CBE_IOPTE_PP_R)) |
0179         CBE_IOPTE_M | CBE_IOPTE_SO_RW |
0180         (window->ioid & CBE_IOPTE_IOID_Mask);
0181 #else
0182     base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
0183         CBE_IOPTE_SO_RW | (window->ioid & CBE_IOPTE_IOID_Mask);
0184 #endif
0185     if (unlikely(attrs & DMA_ATTR_WEAK_ORDERING))
0186         base_pte &= ~CBE_IOPTE_SO_RW;
0187 
0188     io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
0189 
0190     for (i = 0; i < npages; i++, uaddr += (1 << tbl->it_page_shift))
0191         io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask);
0192 
0193     mb();
0194 
0195     invalidate_tce_cache(window->iommu, io_pte, npages);
0196 
0197     pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n",
0198          index, npages, direction, base_pte);
0199     return 0;
0200 }
0201 
0202 static void tce_free_cell(struct iommu_table *tbl, long index, long npages)
0203 {
0204 
0205     int i;
0206     unsigned long *io_pte, pte;
0207     struct iommu_window *window =
0208         container_of(tbl, struct iommu_window, table);
0209 
0210     pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages);
0211 
0212 #ifdef CELL_IOMMU_REAL_UNMAP
0213     pte = 0;
0214 #else
0215     /* spider bridge does PCI reads after freeing - insert a mapping
0216      * to a scratch page instead of an invalid entry */
0217     pte = CBE_IOPTE_PP_R | CBE_IOPTE_M | CBE_IOPTE_SO_RW |
0218         __pa(window->iommu->pad_page) |
0219         (window->ioid & CBE_IOPTE_IOID_Mask);
0220 #endif
0221 
0222     io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
0223 
0224     for (i = 0; i < npages; i++)
0225         io_pte[i] = pte;
0226 
0227     mb();
0228 
0229     invalidate_tce_cache(window->iommu, io_pte, npages);
0230 }
0231 
0232 static irqreturn_t ioc_interrupt(int irq, void *data)
0233 {
0234     unsigned long stat, spf;
0235     struct cbe_iommu *iommu = data;
0236 
0237     stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
0238     spf = stat & IOC_IO_ExcpStat_SPF_Mask;
0239 
0240     /* Might want to rate limit it */
0241     printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat);
0242     printk(KERN_ERR "  V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n",
0243            !!(stat & IOC_IO_ExcpStat_V),
0244            (spf == IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ',
0245            (spf == IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ',
0246            (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write",
0247            (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask));
0248     printk(KERN_ERR "  page=0x%016lx\n",
0249            stat & IOC_IO_ExcpStat_ADDR_Mask);
0250 
0251     /* clear interrupt */
0252     stat &= ~IOC_IO_ExcpStat_V;
0253     out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat);
0254 
0255     return IRQ_HANDLED;
0256 }
0257 
0258 static int __init cell_iommu_find_ioc(int nid, unsigned long *base)
0259 {
0260     struct device_node *np;
0261     struct resource r;
0262 
0263     *base = 0;
0264 
0265     /* First look for new style /be nodes */
0266     for_each_node_by_name(np, "ioc") {
0267         if (of_node_to_nid(np) != nid)
0268             continue;
0269         if (of_address_to_resource(np, 0, &r)) {
0270             printk(KERN_ERR "iommu: can't get address for %pOF\n",
0271                    np);
0272             continue;
0273         }
0274         *base = r.start;
0275         of_node_put(np);
0276         return 0;
0277     }
0278 
0279     /* Ok, let's try the old way */
0280     for_each_node_by_type(np, "cpu") {
0281         const unsigned int *nidp;
0282         const unsigned long *tmp;
0283 
0284         nidp = of_get_property(np, "node-id", NULL);
0285         if (nidp && *nidp == nid) {
0286             tmp = of_get_property(np, "ioc-translation", NULL);
0287             if (tmp) {
0288                 *base = *tmp;
0289                 of_node_put(np);
0290                 return 0;
0291             }
0292         }
0293     }
0294 
0295     return -ENODEV;
0296 }
0297 
0298 static void __init cell_iommu_setup_stab(struct cbe_iommu *iommu,
0299                 unsigned long dbase, unsigned long dsize,
0300                 unsigned long fbase, unsigned long fsize)
0301 {
0302     struct page *page;
0303     unsigned long segments, stab_size;
0304 
0305     segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT;
0306 
0307     pr_debug("%s: iommu[%d]: segments: %lu\n",
0308             __func__, iommu->nid, segments);
0309 
0310     /* set up the segment table */
0311     stab_size = segments * sizeof(unsigned long);
0312     page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size));
0313     BUG_ON(!page);
0314     iommu->stab = page_address(page);
0315     memset(iommu->stab, 0, stab_size);
0316 }
0317 
0318 static unsigned long *__init cell_iommu_alloc_ptab(struct cbe_iommu *iommu,
0319         unsigned long base, unsigned long size, unsigned long gap_base,
0320         unsigned long gap_size, unsigned long page_shift)
0321 {
0322     struct page *page;
0323     int i;
0324     unsigned long reg, segments, pages_per_segment, ptab_size,
0325               n_pte_pages, start_seg, *ptab;
0326 
0327     start_seg = base >> IO_SEGMENT_SHIFT;
0328     segments  = size >> IO_SEGMENT_SHIFT;
0329     pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift);
0330     /* PTEs for each segment must start on a 4K boundary */
0331     pages_per_segment = max(pages_per_segment,
0332                 (1 << 12) / sizeof(unsigned long));
0333 
0334     ptab_size = segments * pages_per_segment * sizeof(unsigned long);
0335     pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __func__,
0336             iommu->nid, ptab_size, get_order(ptab_size));
0337     page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size));
0338     BUG_ON(!page);
0339 
0340     ptab = page_address(page);
0341     memset(ptab, 0, ptab_size);
0342 
0343     /* number of 4K pages needed for a page table */
0344     n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12;
0345 
0346     pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n",
0347             __func__, iommu->nid, iommu->stab, ptab,
0348             n_pte_pages);
0349 
0350     /* initialise the STEs */
0351     reg = IOSTE_V | ((n_pte_pages - 1) << 5);
0352 
0353     switch (page_shift) {
0354     case 12: reg |= IOSTE_PS_4K;  break;
0355     case 16: reg |= IOSTE_PS_64K; break;
0356     case 20: reg |= IOSTE_PS_1M;  break;
0357     case 24: reg |= IOSTE_PS_16M; break;
0358     default: BUG();
0359     }
0360 
0361     gap_base = gap_base >> IO_SEGMENT_SHIFT;
0362     gap_size = gap_size >> IO_SEGMENT_SHIFT;
0363 
0364     pr_debug("Setting up IOMMU stab:\n");
0365     for (i = start_seg; i < (start_seg + segments); i++) {
0366         if (i >= gap_base && i < (gap_base + gap_size)) {
0367             pr_debug("\toverlap at %d, skipping\n", i);
0368             continue;
0369         }
0370         iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) *
0371                     (i - start_seg));
0372         pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]);
0373     }
0374 
0375     return ptab;
0376 }
0377 
0378 static void __init cell_iommu_enable_hardware(struct cbe_iommu *iommu)
0379 {
0380     int ret;
0381     unsigned long reg, xlate_base;
0382     unsigned int virq;
0383 
0384     if (cell_iommu_find_ioc(iommu->nid, &xlate_base))
0385         panic("%s: missing IOC register mappings for node %d\n",
0386               __func__, iommu->nid);
0387 
0388     iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size);
0389     iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset;
0390 
0391     /* ensure that the STEs have updated */
0392     mb();
0393 
0394     /* setup interrupts for the iommu. */
0395     reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
0396     out_be64(iommu->xlate_regs + IOC_IO_ExcpStat,
0397             reg & ~IOC_IO_ExcpStat_V);
0398     out_be64(iommu->xlate_regs + IOC_IO_ExcpMask,
0399             IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE);
0400 
0401     virq = irq_create_mapping(NULL,
0402             IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT));
0403     BUG_ON(!virq);
0404 
0405     ret = request_irq(virq, ioc_interrupt, 0, iommu->name, iommu);
0406     BUG_ON(ret);
0407 
0408     /* set the IOC segment table origin register (and turn on the iommu) */
0409     reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW;
0410     out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg);
0411     in_be64(iommu->xlate_regs + IOC_IOST_Origin);
0412 
0413     /* turn on IO translation */
0414     reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE;
0415     out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg);
0416 }
0417 
0418 static void __init cell_iommu_setup_hardware(struct cbe_iommu *iommu,
0419     unsigned long base, unsigned long size)
0420 {
0421     cell_iommu_setup_stab(iommu, base, size, 0, 0);
0422     iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0,
0423                         IOMMU_PAGE_SHIFT_4K);
0424     cell_iommu_enable_hardware(iommu);
0425 }
0426 
0427 #if 0/* Unused for now */
0428 static struct iommu_window *find_window(struct cbe_iommu *iommu,
0429         unsigned long offset, unsigned long size)
0430 {
0431     struct iommu_window *window;
0432 
0433     /* todo: check for overlapping (but not equal) windows) */
0434 
0435     list_for_each_entry(window, &(iommu->windows), list) {
0436         if (window->offset == offset && window->size == size)
0437             return window;
0438     }
0439 
0440     return NULL;
0441 }
0442 #endif
0443 
0444 static inline u32 cell_iommu_get_ioid(struct device_node *np)
0445 {
0446     const u32 *ioid;
0447 
0448     ioid = of_get_property(np, "ioid", NULL);
0449     if (ioid == NULL) {
0450         printk(KERN_WARNING "iommu: missing ioid for %pOF using 0\n",
0451                np);
0452         return 0;
0453     }
0454 
0455     return *ioid;
0456 }
0457 
0458 static struct iommu_table_ops cell_iommu_ops = {
0459     .set = tce_build_cell,
0460     .clear = tce_free_cell
0461 };
0462 
0463 static struct iommu_window * __init
0464 cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
0465             unsigned long offset, unsigned long size,
0466             unsigned long pte_offset)
0467 {
0468     struct iommu_window *window;
0469     struct page *page;
0470     u32 ioid;
0471 
0472     ioid = cell_iommu_get_ioid(np);
0473 
0474     window = kzalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid);
0475     BUG_ON(window == NULL);
0476 
0477     window->offset = offset;
0478     window->size = size;
0479     window->ioid = ioid;
0480     window->iommu = iommu;
0481 
0482     window->table.it_blocksize = 16;
0483     window->table.it_base = (unsigned long)iommu->ptab;
0484     window->table.it_index = iommu->nid;
0485     window->table.it_page_shift = IOMMU_PAGE_SHIFT_4K;
0486     window->table.it_offset =
0487         (offset >> window->table.it_page_shift) + pte_offset;
0488     window->table.it_size = size >> window->table.it_page_shift;
0489     window->table.it_ops = &cell_iommu_ops;
0490 
0491     if (!iommu_init_table(&window->table, iommu->nid, 0, 0))
0492         panic("Failed to initialize iommu table");
0493 
0494     pr_debug("\tioid      %d\n", window->ioid);
0495     pr_debug("\tblocksize %ld\n", window->table.it_blocksize);
0496     pr_debug("\tbase      0x%016lx\n", window->table.it_base);
0497     pr_debug("\toffset    0x%lx\n", window->table.it_offset);
0498     pr_debug("\tsize      %ld\n", window->table.it_size);
0499 
0500     list_add(&window->list, &iommu->windows);
0501 
0502     if (offset != 0)
0503         return window;
0504 
0505     /* We need to map and reserve the first IOMMU page since it's used
0506      * by the spider workaround. In theory, we only need to do that when
0507      * running on spider but it doesn't really matter.
0508      *
0509      * This code also assumes that we have a window that starts at 0,
0510      * which is the case on all spider based blades.
0511      */
0512     page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0);
0513     BUG_ON(!page);
0514     iommu->pad_page = page_address(page);
0515     clear_page(iommu->pad_page);
0516 
0517     __set_bit(0, window->table.it_map);
0518     tce_build_cell(&window->table, window->table.it_offset, 1,
0519                (unsigned long)iommu->pad_page, DMA_TO_DEVICE, 0);
0520 
0521     return window;
0522 }
0523 
0524 static struct cbe_iommu *cell_iommu_for_node(int nid)
0525 {
0526     int i;
0527 
0528     for (i = 0; i < cbe_nr_iommus; i++)
0529         if (iommus[i].nid == nid)
0530             return &iommus[i];
0531     return NULL;
0532 }
0533 
0534 static unsigned long cell_dma_nommu_offset;
0535 
0536 static unsigned long dma_iommu_fixed_base;
0537 static bool cell_iommu_enabled;
0538 
0539 /* iommu_fixed_is_weak is set if booted with iommu_fixed=weak */
0540 bool iommu_fixed_is_weak;
0541 
0542 static struct iommu_table *cell_get_iommu_table(struct device *dev)
0543 {
0544     struct iommu_window *window;
0545     struct cbe_iommu *iommu;
0546 
0547     /* Current implementation uses the first window available in that
0548      * node's iommu. We -might- do something smarter later though it may
0549      * never be necessary
0550      */
0551     iommu = cell_iommu_for_node(dev_to_node(dev));
0552     if (iommu == NULL || list_empty(&iommu->windows)) {
0553         dev_err(dev, "iommu: missing iommu for %pOF (node %d)\n",
0554                dev->of_node, dev_to_node(dev));
0555         return NULL;
0556     }
0557     window = list_entry(iommu->windows.next, struct iommu_window, list);
0558 
0559     return &window->table;
0560 }
0561 
0562 static u64 cell_iommu_get_fixed_address(struct device *dev);
0563 
0564 static void cell_dma_dev_setup(struct device *dev)
0565 {
0566     if (cell_iommu_enabled) {
0567         u64 addr = cell_iommu_get_fixed_address(dev);
0568 
0569         if (addr != OF_BAD_ADDR)
0570             dev->archdata.dma_offset = addr + dma_iommu_fixed_base;
0571         set_iommu_table_base(dev, cell_get_iommu_table(dev));
0572     } else {
0573         dev->archdata.dma_offset = cell_dma_nommu_offset;
0574     }
0575 }
0576 
0577 static void cell_pci_dma_dev_setup(struct pci_dev *dev)
0578 {
0579     cell_dma_dev_setup(&dev->dev);
0580 }
0581 
0582 static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action,
0583                   void *data)
0584 {
0585     struct device *dev = data;
0586 
0587     /* We are only interested in device addition */
0588     if (action != BUS_NOTIFY_ADD_DEVICE)
0589         return 0;
0590 
0591     if (cell_iommu_enabled)
0592         dev->dma_ops = &dma_iommu_ops;
0593     cell_dma_dev_setup(dev);
0594     return 0;
0595 }
0596 
0597 static struct notifier_block cell_of_bus_notifier = {
0598     .notifier_call = cell_of_bus_notify
0599 };
0600 
0601 static int __init cell_iommu_get_window(struct device_node *np,
0602                      unsigned long *base,
0603                      unsigned long *size)
0604 {
0605     const __be32 *dma_window;
0606     unsigned long index;
0607 
0608     /* Use ibm,dma-window if available, else, hard code ! */
0609     dma_window = of_get_property(np, "ibm,dma-window", NULL);
0610     if (dma_window == NULL) {
0611         *base = 0;
0612         *size = 0x80000000u;
0613         return -ENODEV;
0614     }
0615 
0616     of_parse_dma_window(np, dma_window, &index, base, size);
0617     return 0;
0618 }
0619 
0620 static struct cbe_iommu * __init cell_iommu_alloc(struct device_node *np)
0621 {
0622     struct cbe_iommu *iommu;
0623     int nid, i;
0624 
0625     /* Get node ID */
0626     nid = of_node_to_nid(np);
0627     if (nid < 0) {
0628         printk(KERN_ERR "iommu: failed to get node for %pOF\n",
0629                np);
0630         return NULL;
0631     }
0632     pr_debug("iommu: setting up iommu for node %d (%pOF)\n",
0633          nid, np);
0634 
0635     /* XXX todo: If we can have multiple windows on the same IOMMU, which
0636      * isn't the case today, we probably want here to check whether the
0637      * iommu for that node is already setup.
0638      * However, there might be issue with getting the size right so let's
0639      * ignore that for now. We might want to completely get rid of the
0640      * multiple window support since the cell iommu supports per-page ioids
0641      */
0642 
0643     if (cbe_nr_iommus >= NR_IOMMUS) {
0644         printk(KERN_ERR "iommu: too many IOMMUs detected ! (%pOF)\n",
0645                np);
0646         return NULL;
0647     }
0648 
0649     /* Init base fields */
0650     i = cbe_nr_iommus++;
0651     iommu = &iommus[i];
0652     iommu->stab = NULL;
0653     iommu->nid = nid;
0654     snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i);
0655     INIT_LIST_HEAD(&iommu->windows);
0656 
0657     return iommu;
0658 }
0659 
0660 static void __init cell_iommu_init_one(struct device_node *np,
0661                        unsigned long offset)
0662 {
0663     struct cbe_iommu *iommu;
0664     unsigned long base, size;
0665 
0666     iommu = cell_iommu_alloc(np);
0667     if (!iommu)
0668         return;
0669 
0670     /* Obtain a window for it */
0671     cell_iommu_get_window(np, &base, &size);
0672 
0673     pr_debug("\ttranslating window 0x%lx...0x%lx\n",
0674          base, base + size - 1);
0675 
0676     /* Initialize the hardware */
0677     cell_iommu_setup_hardware(iommu, base, size);
0678 
0679     /* Setup the iommu_table */
0680     cell_iommu_setup_window(iommu, np, base, size,
0681                 offset >> IOMMU_PAGE_SHIFT_4K);
0682 }
0683 
0684 static void __init cell_disable_iommus(void)
0685 {
0686     int node;
0687     unsigned long base, val;
0688     void __iomem *xregs, *cregs;
0689 
0690     /* Make sure IOC translation is disabled on all nodes */
0691     for_each_online_node(node) {
0692         if (cell_iommu_find_ioc(node, &base))
0693             continue;
0694         xregs = ioremap(base, IOC_Reg_Size);
0695         if (xregs == NULL)
0696             continue;
0697         cregs = xregs + IOC_IOCmd_Offset;
0698 
0699         pr_debug("iommu: cleaning up iommu on node %d\n", node);
0700 
0701         out_be64(xregs + IOC_IOST_Origin, 0);
0702         (void)in_be64(xregs + IOC_IOST_Origin);
0703         val = in_be64(cregs + IOC_IOCmd_Cfg);
0704         val &= ~IOC_IOCmd_Cfg_TE;
0705         out_be64(cregs + IOC_IOCmd_Cfg, val);
0706         (void)in_be64(cregs + IOC_IOCmd_Cfg);
0707 
0708         iounmap(xregs);
0709     }
0710 }
0711 
0712 static int __init cell_iommu_init_disabled(void)
0713 {
0714     struct device_node *np = NULL;
0715     unsigned long base = 0, size;
0716 
0717     /* When no iommu is present, we use direct DMA ops */
0718 
0719     /* First make sure all IOC translation is turned off */
0720     cell_disable_iommus();
0721 
0722     /* If we have no Axon, we set up the spider DMA magic offset */
0723     if (of_find_node_by_name(NULL, "axon") == NULL)
0724         cell_dma_nommu_offset = SPIDER_DMA_OFFSET;
0725 
0726     /* Now we need to check to see where the memory is mapped
0727      * in PCI space. We assume that all busses use the same dma
0728      * window which is always the case so far on Cell, thus we
0729      * pick up the first pci-internal node we can find and check
0730      * the DMA window from there.
0731      */
0732     for_each_node_by_name(np, "axon") {
0733         if (np->parent == NULL || np->parent->parent != NULL)
0734             continue;
0735         if (cell_iommu_get_window(np, &base, &size) == 0)
0736             break;
0737     }
0738     if (np == NULL) {
0739         for_each_node_by_name(np, "pci-internal") {
0740             if (np->parent == NULL || np->parent->parent != NULL)
0741                 continue;
0742             if (cell_iommu_get_window(np, &base, &size) == 0)
0743                 break;
0744         }
0745     }
0746     of_node_put(np);
0747 
0748     /* If we found a DMA window, we check if it's big enough to enclose
0749      * all of physical memory. If not, we force enable IOMMU
0750      */
0751     if (np && size < memblock_end_of_DRAM()) {
0752         printk(KERN_WARNING "iommu: force-enabled, dma window"
0753                " (%ldMB) smaller than total memory (%lldMB)\n",
0754                size >> 20, memblock_end_of_DRAM() >> 20);
0755         return -ENODEV;
0756     }
0757 
0758     cell_dma_nommu_offset += base;
0759 
0760     if (cell_dma_nommu_offset != 0)
0761         cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup;
0762 
0763     printk("iommu: disabled, direct DMA offset is 0x%lx\n",
0764            cell_dma_nommu_offset);
0765 
0766     return 0;
0767 }
0768 
0769 /*
0770  *  Fixed IOMMU mapping support
0771  *
0772  *  This code adds support for setting up a fixed IOMMU mapping on certain
0773  *  cell machines. For 64-bit devices this avoids the performance overhead of
0774  *  mapping and unmapping pages at runtime. 32-bit devices are unable to use
0775  *  the fixed mapping.
0776  *
0777  *  The fixed mapping is established at boot, and maps all of physical memory
0778  *  1:1 into device space at some offset. On machines with < 30 GB of memory
0779  *  we setup the fixed mapping immediately above the normal IOMMU window.
0780  *
0781  *  For example a machine with 4GB of memory would end up with the normal
0782  *  IOMMU window from 0-2GB and the fixed mapping window from 2GB to 6GB. In
0783  *  this case a 64-bit device wishing to DMA to 1GB would be told to DMA to
0784  *  3GB, plus any offset required by firmware. The firmware offset is encoded
0785  *  in the "dma-ranges" property.
0786  *
0787  *  On machines with 30GB or more of memory, we are unable to place the fixed
0788  *  mapping above the normal IOMMU window as we would run out of address space.
0789  *  Instead we move the normal IOMMU window to coincide with the hash page
0790  *  table, this region does not need to be part of the fixed mapping as no
0791  *  device should ever be DMA'ing to it. We then setup the fixed mapping
0792  *  from 0 to 32GB.
0793  */
0794 
0795 static u64 cell_iommu_get_fixed_address(struct device *dev)
0796 {
0797     u64 cpu_addr, size, best_size, dev_addr = OF_BAD_ADDR;
0798     struct device_node *np;
0799     const u32 *ranges = NULL;
0800     int i, len, best, naddr, nsize, pna, range_size;
0801 
0802     /* We can be called for platform devices that have no of_node */
0803     np = of_node_get(dev->of_node);
0804     if (!np)
0805         goto out;
0806 
0807     while (1) {
0808         naddr = of_n_addr_cells(np);
0809         nsize = of_n_size_cells(np);
0810         np = of_get_next_parent(np);
0811         if (!np)
0812             break;
0813 
0814         ranges = of_get_property(np, "dma-ranges", &len);
0815 
0816         /* Ignore empty ranges, they imply no translation required */
0817         if (ranges && len > 0)
0818             break;
0819     }
0820 
0821     if (!ranges) {
0822         dev_dbg(dev, "iommu: no dma-ranges found\n");
0823         goto out;
0824     }
0825 
0826     len /= sizeof(u32);
0827 
0828     pna = of_n_addr_cells(np);
0829     range_size = naddr + nsize + pna;
0830 
0831     /* dma-ranges format:
0832      * child addr   : naddr cells
0833      * parent addr  : pna cells
0834      * size     : nsize cells
0835      */
0836     for (i = 0, best = -1, best_size = 0; i < len; i += range_size) {
0837         cpu_addr = of_translate_dma_address(np, ranges + i + naddr);
0838         size = of_read_number(ranges + i + naddr + pna, nsize);
0839 
0840         if (cpu_addr == 0 && size > best_size) {
0841             best = i;
0842             best_size = size;
0843         }
0844     }
0845 
0846     if (best >= 0) {
0847         dev_addr = of_read_number(ranges + best, naddr);
0848     } else
0849         dev_dbg(dev, "iommu: no suitable range found!\n");
0850 
0851 out:
0852     of_node_put(np);
0853 
0854     return dev_addr;
0855 }
0856 
0857 static bool cell_pci_iommu_bypass_supported(struct pci_dev *pdev, u64 mask)
0858 {
0859     return mask == DMA_BIT_MASK(64) &&
0860         cell_iommu_get_fixed_address(&pdev->dev) != OF_BAD_ADDR;
0861 }
0862 
0863 static void __init insert_16M_pte(unsigned long addr, unsigned long *ptab,
0864                unsigned long base_pte)
0865 {
0866     unsigned long segment, offset;
0867 
0868     segment = addr >> IO_SEGMENT_SHIFT;
0869     offset = (addr >> 24) - (segment << IO_PAGENO_BITS(24));
0870     ptab = ptab + (segment * (1 << 12) / sizeof(unsigned long));
0871 
0872     pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n",
0873           addr, ptab, segment, offset);
0874 
0875     ptab[offset] = base_pte | (__pa(addr) & CBE_IOPTE_RPN_Mask);
0876 }
0877 
0878 static void __init cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
0879     struct device_node *np, unsigned long dbase, unsigned long dsize,
0880     unsigned long fbase, unsigned long fsize)
0881 {
0882     unsigned long base_pte, uaddr, ioaddr, *ptab;
0883 
0884     ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize, 24);
0885 
0886     dma_iommu_fixed_base = fbase;
0887 
0888     pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
0889 
0890     base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
0891         (cell_iommu_get_ioid(np) & CBE_IOPTE_IOID_Mask);
0892 
0893     if (iommu_fixed_is_weak)
0894         pr_info("IOMMU: Using weak ordering for fixed mapping\n");
0895     else {
0896         pr_info("IOMMU: Using strong ordering for fixed mapping\n");
0897         base_pte |= CBE_IOPTE_SO_RW;
0898     }
0899 
0900     for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
0901         /* Don't touch the dynamic region */
0902         ioaddr = uaddr + fbase;
0903         if (ioaddr >= dbase && ioaddr < (dbase + dsize)) {
0904             pr_debug("iommu: fixed/dynamic overlap, skipping\n");
0905             continue;
0906         }
0907 
0908         insert_16M_pte(uaddr, ptab, base_pte);
0909     }
0910 
0911     mb();
0912 }
0913 
0914 static int __init cell_iommu_fixed_mapping_init(void)
0915 {
0916     unsigned long dbase, dsize, fbase, fsize, hbase, hend;
0917     struct cbe_iommu *iommu;
0918     struct device_node *np;
0919 
0920     /* The fixed mapping is only supported on axon machines */
0921     np = of_find_node_by_name(NULL, "axon");
0922     of_node_put(np);
0923 
0924     if (!np) {
0925         pr_debug("iommu: fixed mapping disabled, no axons found\n");
0926         return -1;
0927     }
0928 
0929     /* We must have dma-ranges properties for fixed mapping to work */
0930     np = of_find_node_with_property(NULL, "dma-ranges");
0931     of_node_put(np);
0932 
0933     if (!np) {
0934         pr_debug("iommu: no dma-ranges found, no fixed mapping\n");
0935         return -1;
0936     }
0937 
0938     /* The default setup is to have the fixed mapping sit after the
0939      * dynamic region, so find the top of the largest IOMMU window
0940      * on any axon, then add the size of RAM and that's our max value.
0941      * If that is > 32GB we have to do other shennanigans.
0942      */
0943     fbase = 0;
0944     for_each_node_by_name(np, "axon") {
0945         cell_iommu_get_window(np, &dbase, &dsize);
0946         fbase = max(fbase, dbase + dsize);
0947     }
0948 
0949     fbase = ALIGN(fbase, 1 << IO_SEGMENT_SHIFT);
0950     fsize = memblock_phys_mem_size();
0951 
0952     if ((fbase + fsize) <= 0x800000000ul)
0953         hbase = 0; /* use the device tree window */
0954     else {
0955         /* If we're over 32 GB we need to cheat. We can't map all of
0956          * RAM with the fixed mapping, and also fit the dynamic
0957          * region. So try to place the dynamic region where the hash
0958          * table sits, drivers never need to DMA to it, we don't
0959          * need a fixed mapping for that area.
0960          */
0961         if (!htab_address) {
0962             pr_debug("iommu: htab is NULL, on LPAR? Huh?\n");
0963             return -1;
0964         }
0965         hbase = __pa(htab_address);
0966         hend  = hbase + htab_size_bytes;
0967 
0968         /* The window must start and end on a segment boundary */
0969         if ((hbase != ALIGN(hbase, 1 << IO_SEGMENT_SHIFT)) ||
0970             (hend != ALIGN(hend, 1 << IO_SEGMENT_SHIFT))) {
0971             pr_debug("iommu: hash window not segment aligned\n");
0972             return -1;
0973         }
0974 
0975         /* Check the hash window fits inside the real DMA window */
0976         for_each_node_by_name(np, "axon") {
0977             cell_iommu_get_window(np, &dbase, &dsize);
0978 
0979             if (hbase < dbase || (hend > (dbase + dsize))) {
0980                 pr_debug("iommu: hash window doesn't fit in"
0981                      "real DMA window\n");
0982                 of_node_put(np);
0983                 return -1;
0984             }
0985         }
0986 
0987         fbase = 0;
0988     }
0989 
0990     /* Setup the dynamic regions */
0991     for_each_node_by_name(np, "axon") {
0992         iommu = cell_iommu_alloc(np);
0993         BUG_ON(!iommu);
0994 
0995         if (hbase == 0)
0996             cell_iommu_get_window(np, &dbase, &dsize);
0997         else {
0998             dbase = hbase;
0999             dsize = htab_size_bytes;
1000         }
1001 
1002         printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx "
1003             "fixed window 0x%lx-0x%lx\n", iommu->nid, dbase,
1004              dbase + dsize, fbase, fbase + fsize);
1005 
1006         cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize);
1007         iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0,
1008                             IOMMU_PAGE_SHIFT_4K);
1009         cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize,
1010                          fbase, fsize);
1011         cell_iommu_enable_hardware(iommu);
1012         cell_iommu_setup_window(iommu, np, dbase, dsize, 0);
1013     }
1014 
1015     cell_pci_controller_ops.iommu_bypass_supported =
1016         cell_pci_iommu_bypass_supported;
1017     return 0;
1018 }
1019 
1020 static int iommu_fixed_disabled;
1021 
1022 static int __init setup_iommu_fixed(char *str)
1023 {
1024     struct device_node *pciep;
1025 
1026     if (strcmp(str, "off") == 0)
1027         iommu_fixed_disabled = 1;
1028 
1029     /* If we can find a pcie-endpoint in the device tree assume that
1030      * we're on a triblade or a CAB so by default the fixed mapping
1031      * should be set to be weakly ordered; but only if the boot
1032      * option WASN'T set for strong ordering
1033      */
1034     pciep = of_find_node_by_type(NULL, "pcie-endpoint");
1035 
1036     if (strcmp(str, "weak") == 0 || (pciep && strcmp(str, "strong") != 0))
1037         iommu_fixed_is_weak = true;
1038 
1039     of_node_put(pciep);
1040 
1041     return 1;
1042 }
1043 __setup("iommu_fixed=", setup_iommu_fixed);
1044 
1045 static int __init cell_iommu_init(void)
1046 {
1047     struct device_node *np;
1048 
1049     /* If IOMMU is disabled or we have little enough RAM to not need
1050      * to enable it, we setup a direct mapping.
1051      *
1052      * Note: should we make sure we have the IOMMU actually disabled ?
1053      */
1054     if (iommu_is_off ||
1055         (!iommu_force_on && memblock_end_of_DRAM() <= 0x80000000ull))
1056         if (cell_iommu_init_disabled() == 0)
1057             goto bail;
1058 
1059     /* Setup various callbacks */
1060     cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup;
1061 
1062     if (!iommu_fixed_disabled && cell_iommu_fixed_mapping_init() == 0)
1063         goto done;
1064 
1065     /* Create an iommu for each /axon node.  */
1066     for_each_node_by_name(np, "axon") {
1067         if (np->parent == NULL || np->parent->parent != NULL)
1068             continue;
1069         cell_iommu_init_one(np, 0);
1070     }
1071 
1072     /* Create an iommu for each toplevel /pci-internal node for
1073      * old hardware/firmware
1074      */
1075     for_each_node_by_name(np, "pci-internal") {
1076         if (np->parent == NULL || np->parent->parent != NULL)
1077             continue;
1078         cell_iommu_init_one(np, SPIDER_DMA_OFFSET);
1079     }
1080  done:
1081     /* Setup default PCI iommu ops */
1082     set_pci_dma_ops(&dma_iommu_ops);
1083     cell_iommu_enabled = true;
1084  bail:
1085     /* Register callbacks on OF platform device addition/removal
1086      * to handle linking them to the right DMA operations
1087      */
1088     bus_register_notifier(&platform_bus_type, &cell_of_bus_notifier);
1089 
1090     return 0;
1091 }
1092 machine_arch_initcall(cell, cell_iommu_init);
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