platforms/cell/interrupt.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef ASM_CELL_PIC_H
0003 #define ASM_CELL_PIC_H
0004 #ifdef __KERNEL__
0005 /*
0006  * Mapping of IIC pending bits into per-node interrupt numbers.
0007  *
0008  * Interrupt numbers are in the range 0...0x1ff where the top bit
0009  * (0x100) represent the source node. Only 2 nodes are supported with
0010  * the current code though it's trivial to extend that if necessary using
0011  * higher level bits
0012  *
0013  * The bottom 8 bits are split into 2 type bits and 6 data bits that
0014  * depend on the type:
0015  *
0016  * 00 (0x00 | data) : normal interrupt. data is (class << 4) | source
0017  * 01 (0x40 | data) : IO exception. data is the exception number as
0018  *                    defined by bit numbers in IIC_SR
0019  * 10 (0x80 | data) : IPI. data is the IPI number (obtained from the priority)
0020  *                    and node is always 0 (IPIs are per-cpu, their source is
0021  *                    not relevant)
0022  * 11 (0xc0 | data) : reserved
0023  *
0024  * In addition, interrupt number 0x80000000 is defined as always invalid
0025  * (that is the node field is expected to never extend to move than 23 bits)
0026  *
0027  */
0028
0029 enum {
0030     IIC_IRQ_INVALID     = 0x80000000u,
0031     IIC_IRQ_NODE_MASK   = 0x100,
0032     IIC_IRQ_NODE_SHIFT  = 8,
0033     IIC_IRQ_MAX     = 0x1ff,
0034     IIC_IRQ_TYPE_MASK   = 0xc0,
0035     IIC_IRQ_TYPE_NORMAL = 0x00,
0036     IIC_IRQ_TYPE_IOEXC  = 0x40,
0037     IIC_IRQ_TYPE_IPI    = 0x80,
0038     IIC_IRQ_CLASS_SHIFT = 4,
0039     IIC_IRQ_CLASS_0     = 0x00,
0040     IIC_IRQ_CLASS_1     = 0x10,
0041     IIC_IRQ_CLASS_2     = 0x20,
0042     IIC_SOURCE_COUNT    = 0x200,
0043
0044     /* Here are defined the various source/dest units. Avoid using those
0045      * definitions if you can, they are mostly here for reference
0046      */
0047     IIC_UNIT_SPU_0      = 0x4,
0048     IIC_UNIT_SPU_1      = 0x7,
0049     IIC_UNIT_SPU_2      = 0x3,
0050     IIC_UNIT_SPU_3      = 0x8,
0051     IIC_UNIT_SPU_4      = 0x2,
0052     IIC_UNIT_SPU_5      = 0x9,
0053     IIC_UNIT_SPU_6      = 0x1,
0054     IIC_UNIT_SPU_7      = 0xa,
0055     IIC_UNIT_IOC_0      = 0x0,
0056     IIC_UNIT_IOC_1      = 0xb,
0057     IIC_UNIT_THREAD_0   = 0xe, /* target only */
0058     IIC_UNIT_THREAD_1   = 0xf, /* target only */
0059     IIC_UNIT_IIC        = 0xe, /* source only (IO exceptions) */
0060
0061     /* Base numbers for the external interrupts */
0062     IIC_IRQ_EXT_IOIF0   =
0063         IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_0,
0064     IIC_IRQ_EXT_IOIF1   =
0065         IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_1,
0066
0067     /* Base numbers for the IIC_ISR interrupts */
0068     IIC_IRQ_IOEX_TMI    = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 63,
0069     IIC_IRQ_IOEX_PMI    = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 62,
0070     IIC_IRQ_IOEX_ATI    = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 61,
0071     IIC_IRQ_IOEX_MATBFI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 60,
0072     IIC_IRQ_IOEX_ELDI   = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 59,
0073
0074     /* Which bits in IIC_ISR are edge sensitive */
0075     IIC_ISR_EDGE_MASK   = 0x4ul,
0076 };
0077
0078 extern void iic_init_IRQ(void);
0079 extern void iic_message_pass(int cpu, int msg);
0080 extern void iic_request_IPIs(void);
0081 extern void iic_setup_cpu(void);
0082
0083 extern u8 iic_get_target_id(int cpu);
0084
0085 extern void spider_init_IRQ(void);
0086
0087 extern void iic_set_interrupt_routing(int cpu, int thread, int priority);
0088
0089 #endif
0090 #endif /* ASM_CELL_PIC_H */