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0007 #include <linux/interrupt.h>
0008 #include <linux/irq.h>
0009 #include <linux/kernel.h>
0010 #include <linux/pci.h>
0011 #include <linux/msi.h>
0012 #include <linux/export.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/slab.h>
0015 #include <linux/debugfs.h>
0016 #include <linux/of_irq.h>
0017
0018 #include <asm/dcr.h>
0019 #include <asm/machdep.h>
0020
0021 #include "cell.h"
0022
0023
0024
0025
0026 #define MSIC_CTRL_REG 0x0
0027
0028
0029 #define MSIC_BASE_ADDR_HI_REG 0x3
0030 #define MSIC_BASE_ADDR_LO_REG 0x4
0031
0032
0033 #define MSIC_READ_OFFSET_REG 0x5
0034 #define MSIC_WRITE_OFFSET_REG 0x6
0035
0036
0037
0038 #define MSIC_CTRL_ENABLE 0x0001
0039 #define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
0040 #define MSIC_CTRL_IRQ_ENABLE 0x0008
0041 #define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
0042
0043
0044
0045
0046
0047 #define MSIC_FIFO_SIZE_SHIFT 16
0048 #define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
0049
0050
0051
0052
0053
0054 #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
0055
0056
0057
0058
0059
0060 #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
0061
0062
0063 #define MSIC_FIFO_ENTRY_SIZE 0x10
0064
0065
0066 struct axon_msic {
0067 struct irq_domain *irq_domain;
0068 __le32 *fifo_virt;
0069 dma_addr_t fifo_phys;
0070 dcr_host_t dcr_host;
0071 u32 read_offset;
0072 #ifdef DEBUG
0073 u32 __iomem *trigger;
0074 #endif
0075 };
0076
0077 #ifdef DEBUG
0078 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
0079 #else
0080 static inline void axon_msi_debug_setup(struct device_node *dn,
0081 struct axon_msic *msic) { }
0082 #endif
0083
0084
0085 static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
0086 {
0087 pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
0088
0089 dcr_write(msic->dcr_host, dcr_n, val);
0090 }
0091
0092 static void axon_msi_cascade(struct irq_desc *desc)
0093 {
0094 struct irq_chip *chip = irq_desc_get_chip(desc);
0095 struct axon_msic *msic = irq_desc_get_handler_data(desc);
0096 u32 write_offset, msi;
0097 int idx;
0098 int retry = 0;
0099
0100 write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
0101 pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
0102
0103
0104 write_offset &= MSIC_FIFO_SIZE_MASK;
0105
0106 while (msic->read_offset != write_offset && retry < 100) {
0107 idx = msic->read_offset / sizeof(__le32);
0108 msi = le32_to_cpu(msic->fifo_virt[idx]);
0109 msi &= 0xFFFF;
0110
0111 pr_devel("axon_msi: woff %x roff %x msi %x\n",
0112 write_offset, msic->read_offset, msi);
0113
0114 if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
0115 generic_handle_irq(msi);
0116 msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
0117 } else {
0118
0119
0120
0121
0122
0123
0124 udelay(1);
0125 retry++;
0126 pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
0127 continue;
0128 }
0129
0130 if (retry) {
0131 pr_devel("axon_msi: late irq 0x%x, retry %d\n",
0132 msi, retry);
0133 retry = 0;
0134 }
0135
0136 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
0137 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
0138 }
0139
0140 if (retry) {
0141 printk(KERN_WARNING "axon_msi: irq timed out\n");
0142
0143 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
0144 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
0145 }
0146
0147 chip->irq_eoi(&desc->irq_data);
0148 }
0149
0150 static struct axon_msic *find_msi_translator(struct pci_dev *dev)
0151 {
0152 struct irq_domain *irq_domain;
0153 struct device_node *dn, *tmp;
0154 const phandle *ph;
0155 struct axon_msic *msic = NULL;
0156
0157 dn = of_node_get(pci_device_to_OF_node(dev));
0158 if (!dn) {
0159 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
0160 return NULL;
0161 }
0162
0163 for (; dn; dn = of_get_next_parent(dn)) {
0164 ph = of_get_property(dn, "msi-translator", NULL);
0165 if (ph)
0166 break;
0167 }
0168
0169 if (!ph) {
0170 dev_dbg(&dev->dev,
0171 "axon_msi: no msi-translator property found\n");
0172 goto out_error;
0173 }
0174
0175 tmp = dn;
0176 dn = of_find_node_by_phandle(*ph);
0177 of_node_put(tmp);
0178 if (!dn) {
0179 dev_dbg(&dev->dev,
0180 "axon_msi: msi-translator doesn't point to a node\n");
0181 goto out_error;
0182 }
0183
0184 irq_domain = irq_find_host(dn);
0185 if (!irq_domain) {
0186 dev_dbg(&dev->dev, "axon_msi: no irq_domain found for node %pOF\n",
0187 dn);
0188 goto out_error;
0189 }
0190
0191 msic = irq_domain->host_data;
0192
0193 out_error:
0194 of_node_put(dn);
0195
0196 return msic;
0197 }
0198
0199 static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
0200 {
0201 struct device_node *dn;
0202 int len;
0203 const u32 *prop;
0204
0205 dn = of_node_get(pci_device_to_OF_node(dev));
0206 if (!dn) {
0207 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
0208 return -ENODEV;
0209 }
0210
0211 for (; dn; dn = of_get_next_parent(dn)) {
0212 if (!dev->no_64bit_msi) {
0213 prop = of_get_property(dn, "msi-address-64", &len);
0214 if (prop)
0215 break;
0216 }
0217
0218 prop = of_get_property(dn, "msi-address-32", &len);
0219 if (prop)
0220 break;
0221 }
0222
0223 if (!prop) {
0224 dev_dbg(&dev->dev,
0225 "axon_msi: no msi-address-(32|64) properties found\n");
0226 of_node_put(dn);
0227 return -ENOENT;
0228 }
0229
0230 switch (len) {
0231 case 8:
0232 msg->address_hi = prop[0];
0233 msg->address_lo = prop[1];
0234 break;
0235 case 4:
0236 msg->address_hi = 0;
0237 msg->address_lo = prop[0];
0238 break;
0239 default:
0240 dev_dbg(&dev->dev,
0241 "axon_msi: malformed msi-address-(32|64) property\n");
0242 of_node_put(dn);
0243 return -EINVAL;
0244 }
0245
0246 of_node_put(dn);
0247
0248 return 0;
0249 }
0250
0251 static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
0252 {
0253 unsigned int virq, rc;
0254 struct msi_desc *entry;
0255 struct msi_msg msg;
0256 struct axon_msic *msic;
0257
0258 msic = find_msi_translator(dev);
0259 if (!msic)
0260 return -ENODEV;
0261
0262 rc = setup_msi_msg_address(dev, &msg);
0263 if (rc)
0264 return rc;
0265
0266 msi_for_each_desc(entry, &dev->dev, MSI_DESC_NOTASSOCIATED) {
0267 virq = irq_create_direct_mapping(msic->irq_domain);
0268 if (!virq) {
0269 dev_warn(&dev->dev,
0270 "axon_msi: virq allocation failed!\n");
0271 return -1;
0272 }
0273 dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
0274
0275 irq_set_msi_desc(virq, entry);
0276 msg.data = virq;
0277 pci_write_msi_msg(virq, &msg);
0278 }
0279
0280 return 0;
0281 }
0282
0283 static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
0284 {
0285 struct msi_desc *entry;
0286
0287 dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
0288
0289 msi_for_each_desc(entry, &dev->dev, MSI_DESC_ASSOCIATED) {
0290 irq_set_msi_desc(entry->irq, NULL);
0291 irq_dispose_mapping(entry->irq);
0292 }
0293 }
0294
0295 static struct irq_chip msic_irq_chip = {
0296 .irq_mask = pci_msi_mask_irq,
0297 .irq_unmask = pci_msi_unmask_irq,
0298 .irq_shutdown = pci_msi_mask_irq,
0299 .name = "AXON-MSI",
0300 };
0301
0302 static int msic_host_map(struct irq_domain *h, unsigned int virq,
0303 irq_hw_number_t hw)
0304 {
0305 irq_set_chip_data(virq, h->host_data);
0306 irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
0307
0308 return 0;
0309 }
0310
0311 static const struct irq_domain_ops msic_host_ops = {
0312 .map = msic_host_map,
0313 };
0314
0315 static void axon_msi_shutdown(struct platform_device *device)
0316 {
0317 struct axon_msic *msic = dev_get_drvdata(&device->dev);
0318 u32 tmp;
0319
0320 pr_devel("axon_msi: disabling %pOF\n",
0321 irq_domain_get_of_node(msic->irq_domain));
0322 tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
0323 tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
0324 msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
0325 }
0326
0327 static int axon_msi_probe(struct platform_device *device)
0328 {
0329 struct device_node *dn = device->dev.of_node;
0330 struct axon_msic *msic;
0331 unsigned int virq;
0332 int dcr_base, dcr_len;
0333
0334 pr_devel("axon_msi: setting up dn %pOF\n", dn);
0335
0336 msic = kzalloc(sizeof(*msic), GFP_KERNEL);
0337 if (!msic) {
0338 printk(KERN_ERR "axon_msi: couldn't allocate msic for %pOF\n",
0339 dn);
0340 goto out;
0341 }
0342
0343 dcr_base = dcr_resource_start(dn, 0);
0344 dcr_len = dcr_resource_len(dn, 0);
0345
0346 if (dcr_base == 0 || dcr_len == 0) {
0347 printk(KERN_ERR
0348 "axon_msi: couldn't parse dcr properties on %pOF\n",
0349 dn);
0350 goto out_free_msic;
0351 }
0352
0353 msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
0354 if (!DCR_MAP_OK(msic->dcr_host)) {
0355 printk(KERN_ERR "axon_msi: dcr_map failed for %pOF\n",
0356 dn);
0357 goto out_free_msic;
0358 }
0359
0360 msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
0361 &msic->fifo_phys, GFP_KERNEL);
0362 if (!msic->fifo_virt) {
0363 printk(KERN_ERR "axon_msi: couldn't allocate fifo for %pOF\n",
0364 dn);
0365 goto out_free_msic;
0366 }
0367
0368 virq = irq_of_parse_and_map(dn, 0);
0369 if (!virq) {
0370 printk(KERN_ERR "axon_msi: irq parse and map failed for %pOF\n",
0371 dn);
0372 goto out_free_fifo;
0373 }
0374 memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
0375
0376
0377 msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
0378 if (!msic->irq_domain) {
0379 printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %pOF\n",
0380 dn);
0381 goto out_free_fifo;
0382 }
0383
0384 irq_set_handler_data(virq, msic);
0385 irq_set_chained_handler(virq, axon_msi_cascade);
0386 pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
0387
0388
0389 msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
0390 msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
0391 msic->fifo_phys & 0xFFFFFFFF);
0392 msic_dcr_write(msic, MSIC_CTRL_REG,
0393 MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
0394 MSIC_CTRL_FIFO_SIZE);
0395
0396 msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
0397 & MSIC_FIFO_SIZE_MASK;
0398
0399 dev_set_drvdata(&device->dev, msic);
0400
0401 cell_pci_controller_ops.setup_msi_irqs = axon_msi_setup_msi_irqs;
0402 cell_pci_controller_ops.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
0403
0404 axon_msi_debug_setup(dn, msic);
0405
0406 printk(KERN_DEBUG "axon_msi: setup MSIC on %pOF\n", dn);
0407
0408 return 0;
0409
0410 out_free_fifo:
0411 dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
0412 msic->fifo_phys);
0413 out_free_msic:
0414 kfree(msic);
0415 out:
0416
0417 return -1;
0418 }
0419
0420 static const struct of_device_id axon_msi_device_id[] = {
0421 {
0422 .compatible = "ibm,axon-msic"
0423 },
0424 {}
0425 };
0426
0427 static struct platform_driver axon_msi_driver = {
0428 .probe = axon_msi_probe,
0429 .shutdown = axon_msi_shutdown,
0430 .driver = {
0431 .name = "axon-msi",
0432 .of_match_table = axon_msi_device_id,
0433 },
0434 };
0435
0436 static int __init axon_msi_init(void)
0437 {
0438 return platform_driver_register(&axon_msi_driver);
0439 }
0440 subsys_initcall(axon_msi_init);
0441
0442
0443 #ifdef DEBUG
0444 static int msic_set(void *data, u64 val)
0445 {
0446 struct axon_msic *msic = data;
0447 out_le32(msic->trigger, val);
0448 return 0;
0449 }
0450
0451 static int msic_get(void *data, u64 *val)
0452 {
0453 *val = 0;
0454 return 0;
0455 }
0456
0457 DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
0458
0459 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
0460 {
0461 char name[8];
0462 u64 addr;
0463
0464 addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
0465 if (addr == OF_BAD_ADDR) {
0466 pr_devel("axon_msi: couldn't translate reg property\n");
0467 return;
0468 }
0469
0470 msic->trigger = ioremap(addr, 0x4);
0471 if (!msic->trigger) {
0472 pr_devel("axon_msi: ioremap failed\n");
0473 return;
0474 }
0475
0476 snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
0477
0478 debugfs_create_file(name, 0600, arch_debugfs_dir, msic, &fops_msic);
0479 }
0480 #endif