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OSCL-LXR

 
 

    


0001 # SPDX-License-Identifier: GPL-2.0
0002 config PPC_CELL
0003         select PPC_64S_HASH_MMU if PPC64
0004         bool
0005 
0006 config PPC_CELL_COMMON
0007         bool
0008         select PPC_CELL
0009         select PPC_DCR_MMIO
0010         select PPC_INDIRECT_PIO
0011         select PPC_INDIRECT_MMIO
0012         select PPC_HASH_MMU_NATIVE
0013         select PPC_RTAS
0014         select IRQ_EDGE_EOI_HANDLER
0015 
0016 config PPC_CELL_NATIVE
0017         bool
0018         select PPC_CELL_COMMON
0019         select MPIC
0020         select PPC_IO_WORKAROUNDS
0021         select IBM_EMAC_EMAC4 if IBM_EMAC
0022         select IBM_EMAC_RGMII if IBM_EMAC
0023         select IBM_EMAC_ZMII if IBM_EMAC #test only
0024         select IBM_EMAC_TAH if IBM_EMAC  #test only
0025 
0026 config PPC_IBM_CELL_BLADE
0027         bool "IBM Cell Blade"
0028         depends on PPC64 && PPC_BOOK3S && CPU_BIG_ENDIAN
0029         select PPC_CELL_NATIVE
0030         select PPC_OF_PLATFORM_PCI
0031         select FORCE_PCI
0032         select MMIO_NVRAM
0033         select PPC_UDBG_16550
0034         select UDBG_RTAS_CONSOLE
0035 
0036 config AXON_MSI
0037         bool
0038         depends on PPC_IBM_CELL_BLADE && PCI_MSI
0039         select IRQ_DOMAIN_NOMAP
0040         default y
0041 
0042 menu "Cell Broadband Engine options"
0043         depends on PPC_CELL
0044 
0045 config SPU_FS
0046         tristate "SPU file system"
0047         default m
0048         depends on PPC_CELL
0049         depends on COREDUMP
0050         select SPU_BASE
0051         help
0052           The SPU file system is used to access Synergistic Processing
0053           Units on machines implementing the Broadband Processor
0054           Architecture.
0055 
0056 config SPU_BASE
0057         bool
0058         select PPC_COPRO_BASE
0059 
0060 config CBE_RAS
0061         bool "RAS features for bare metal Cell BE"
0062         depends on PPC_CELL_NATIVE
0063         default y
0064 
0065 config PPC_IBM_CELL_RESETBUTTON
0066         bool "IBM Cell Blade Pinhole reset button"
0067         depends on CBE_RAS && PPC_IBM_CELL_BLADE
0068         default y
0069         help
0070           Support Pinhole Resetbutton on IBM Cell blades.
0071           This adds a method to trigger system reset via front panel pinhole button.
0072 
0073 config PPC_IBM_CELL_POWERBUTTON
0074         tristate "IBM Cell Blade power button"
0075         depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
0076         default y
0077         help
0078           Support Powerbutton on IBM Cell blades.
0079           This will enable the powerbutton as an input device.
0080 
0081 config CBE_THERM
0082         tristate "CBE thermal support"
0083         default m
0084         depends on CBE_RAS && SPU_BASE
0085 
0086 config PPC_PMI
0087         tristate
0088         default y
0089         depends on CPU_FREQ_CBE_PMI || PPC_IBM_CELL_POWERBUTTON
0090         help
0091           PMI (Platform Management Interrupt) is a way to
0092           communicate with the BMC (Baseboard Management Controller).
0093           It is used in some IBM Cell blades.
0094 
0095 config CBE_CPUFREQ_SPU_GOVERNOR
0096         tristate "CBE frequency scaling based on SPU usage"
0097         depends on SPU_FS && CPU_FREQ
0098         default m
0099         help
0100           This governor checks for spu usage to adjust the cpu frequency.
0101           If no spu is running on a given cpu, that cpu will be throttled to
0102           the minimal possible frequency.
0103 
0104 endmenu