platforms/86xx/mpc86xx_smp.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Author: Xianghua Xiao <x.xiao@freescale.com>
0004  *         Zhang Wei <wei.zhang@freescale.com>
0005  *
0006  * Copyright 2006 Freescale Semiconductor Inc.
0007  */
0008
0009 #include <linux/stddef.h>
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pgtable.h>
0014
0015 #include <asm/code-patching.h>
0016 #include <asm/page.h>
0017 #include <asm/pci-bridge.h>
0018 #include <asm/mpic.h>
0019 #include <asm/cacheflush.h>
0020 #include <asm/inst.h>
0021
0022 #include <sysdev/fsl_soc.h>
0023
0024 #include "mpc86xx.h"
0025
0026 extern void __secondary_start_mpc86xx(void);
0027
0028 #define MCM_PORT_CONFIG_OFFSET  0x10
0029
0030 /* Offset from CCSRBAR */
0031 #define MPC86xx_MCM_OFFSET      (0x1000)
0032 #define MPC86xx_MCM_SIZE        (0x1000)
0033
0034 static void __init
0035 smp_86xx_release_core(int nr)
0036 {
0037     __be32 __iomem *mcm_vaddr;
0038     unsigned long pcr;
0039
0040     if (nr < 0 || nr >= NR_CPUS)
0041         return;
0042
0043     /*
0044      * Startup Core #nr.
0045      */
0046     mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,
0047                 MPC86xx_MCM_SIZE);
0048     pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2));
0049     pcr |= 1 << (nr + 24);
0050     out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr);
0051
0052     iounmap(mcm_vaddr);
0053 }
0054
0055
0056 static int __init
0057 smp_86xx_kick_cpu(int nr)
0058 {
0059     unsigned int save_vector;
0060     unsigned long target, flags;
0061     int n = 0;
0062     unsigned int *vector = (unsigned int *)(KERNELBASE + 0x100);
0063
0064     if (nr < 0 || nr >= NR_CPUS)
0065         return -ENOENT;
0066
0067     pr_debug("smp_86xx_kick_cpu: kick CPU #%d\n", nr);
0068
0069     local_irq_save(flags);
0070
0071     /* Save reset vector */
0072     save_vector = *vector;
0073
0074     /* Setup fake reset vector to call __secondary_start_mpc86xx. */
0075     target = (unsigned long) __secondary_start_mpc86xx;
0076     patch_branch(vector, target, BRANCH_SET_LINK);
0077
0078     /* Kick that CPU */
0079     smp_86xx_release_core(nr);
0080
0081     /* Wait a bit for the CPU to take the exception. */
0082     while ((__secondary_hold_acknowledge != nr) && (n++, n < 1000))
0083         mdelay(1);
0084
0085     /* Restore the exception vector */
0086     patch_instruction(vector, ppc_inst(save_vector));
0087
0088     local_irq_restore(flags);
0089
0090     pr_debug("wait CPU #%d for %d msecs.\n", nr, n);
0091
0092     return 0;
0093 }
0094
0095
0096 static void __init
0097 smp_86xx_setup_cpu(int cpu_nr)
0098 {
0099     mpic_setup_this_cpu();
0100 }
0101
0102
0103 struct smp_ops_t smp_86xx_ops = {
0104     .cause_nmi_ipi = NULL,
0105     .message_pass = smp_mpic_message_pass,
0106     .probe = smp_mpic_probe,
0107     .kick_cpu = smp_86xx_kick_cpu,
0108     .setup_cpu = smp_86xx_setup_cpu,
0109     .take_timebase = smp_generic_take_timebase,
0110     .give_timebase = smp_generic_give_timebase,
0111 };
0112
0113
0114 void __init
0115 mpc86xx_smp_init(void)
0116 {
0117     smp_ops = &smp_86xx_ops;
0118 }