platforms/86xx/gef_sbc610.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * GE SBC610 board support
0004  *
0005  * Author: Martyn Welch <martyn.welch@ge.com>
0006  *
0007  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
0008  *
0009  * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
0010  * Copyright 2006 Freescale Semiconductor Inc.
0011  *
0012  * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
0013  */
0014
0015 #include <linux/stddef.h>
0016 #include <linux/kernel.h>
0017 #include <linux/pci.h>
0018 #include <linux/kdev_t.h>
0019 #include <linux/delay.h>
0020 #include <linux/seq_file.h>
0021 #include <linux/of_address.h>
0022 #include <linux/of_platform.h>
0023
0024 #include <asm/time.h>
0025 #include <asm/machdep.h>
0026 #include <asm/pci-bridge.h>
0027 #include <mm/mmu_decl.h>
0028 #include <asm/udbg.h>
0029
0030 #include <asm/mpic.h>
0031 #include <asm/nvram.h>
0032
0033 #include <sysdev/fsl_pci.h>
0034 #include <sysdev/fsl_soc.h>
0035 #include <sysdev/ge/ge_pic.h>
0036
0037 #include "mpc86xx.h"
0038
0039 #undef DEBUG
0040
0041 #ifdef DEBUG
0042 #define DBG (fmt...) do { printk(KERN_ERR "SBC610: " fmt); } while (0)
0043 #else
0044 #define DBG (fmt...) do { } while (0)
0045 #endif
0046
0047 void __iomem *sbc610_regs;
0048
0049 static void __init gef_sbc610_init_irq(void)
0050 {
0051     struct device_node *cascade_node = NULL;
0052
0053     mpc86xx_init_irq();
0054
0055     /*
0056      * There is a simple interrupt handler in the main FPGA, this needs
0057      * to be cascaded into the MPIC
0058      */
0059     cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
0060     if (!cascade_node) {
0061         printk(KERN_WARNING "SBC610: No FPGA PIC\n");
0062         return;
0063     }
0064
0065     gef_pic_init(cascade_node);
0066     of_node_put(cascade_node);
0067 }
0068
0069 static void __init gef_sbc610_setup_arch(void)
0070 {
0071     struct device_node *regs;
0072
0073     printk(KERN_INFO "GE Intelligent Platforms SBC610 6U VPX SBC\n");
0074
0075 #ifdef CONFIG_SMP
0076     mpc86xx_smp_init();
0077 #endif
0078
0079     fsl_pci_assign_primary();
0080
0081     /* Remap basic board registers */
0082     regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
0083     if (regs) {
0084         sbc610_regs = of_iomap(regs, 0);
0085         if (sbc610_regs == NULL)
0086             printk(KERN_WARNING "Unable to map board registers\n");
0087         of_node_put(regs);
0088     }
0089
0090 #if defined(CONFIG_MMIO_NVRAM)
0091     mmio_nvram_init();
0092 #endif
0093 }
0094
0095 /* Return the PCB revision */
0096 static unsigned int gef_sbc610_get_pcb_rev(void)
0097 {
0098     unsigned int reg;
0099
0100     reg = ioread32(sbc610_regs);
0101     return (reg >> 8) & 0xff;
0102 }
0103
0104 /* Return the board (software) revision */
0105 static unsigned int gef_sbc610_get_board_rev(void)
0106 {
0107     unsigned int reg;
0108
0109     reg = ioread32(sbc610_regs);
0110     return (reg >> 16) & 0xff;
0111 }
0112
0113 /* Return the FPGA revision */
0114 static unsigned int gef_sbc610_get_fpga_rev(void)
0115 {
0116     unsigned int reg;
0117
0118     reg = ioread32(sbc610_regs);
0119     return (reg >> 24) & 0xf;
0120 }
0121
0122 static void gef_sbc610_show_cpuinfo(struct seq_file *m)
0123 {
0124     uint svid = mfspr(SPRN_SVR);
0125
0126     seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
0127
0128     seq_printf(m, "Revision\t: %u%c\n", gef_sbc610_get_pcb_rev(),
0129         ('A' + gef_sbc610_get_board_rev() - 1));
0130     seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev());
0131
0132     seq_printf(m, "SVR\t\t: 0x%x\n", svid);
0133 }
0134
0135 static void gef_sbc610_nec_fixup(struct pci_dev *pdev)
0136 {
0137     unsigned int val;
0138
0139     /* Do not do the fixup on other platforms! */
0140     if (!machine_is(gef_sbc610))
0141         return;
0142
0143     printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
0144
0145     /* Ensure ports 1, 2, 3, 4 & 5 are enabled */
0146     pci_read_config_dword(pdev, 0xe0, &val);
0147     pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5);
0148
0149     /* System clock is 48-MHz Oscillator and EHCI Enabled. */
0150     pci_write_config_dword(pdev, 0xe4, 1 << 5);
0151 }
0152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
0153     gef_sbc610_nec_fixup);
0154
0155 /*
0156  * Called very early, device-tree isn't unflattened
0157  *
0158  * This function is called to determine whether the BSP is compatible with the
0159  * supplied device-tree, which is assumed to be the correct one for the actual
0160  * board. It is expected that, in the future, a kernel may support multiple
0161  * boards.
0162  */
0163 static int __init gef_sbc610_probe(void)
0164 {
0165     if (of_machine_is_compatible("gef,sbc610"))
0166         return 1;
0167
0168     return 0;
0169 }
0170
0171 machine_arch_initcall(gef_sbc610, mpc86xx_common_publish_devices);
0172
0173 define_machine(gef_sbc610) {
0174     .name           = "GE SBC610",
0175     .probe          = gef_sbc610_probe,
0176     .setup_arch     = gef_sbc610_setup_arch,
0177     .init_IRQ       = gef_sbc610_init_irq,
0178     .show_cpuinfo       = gef_sbc610_show_cpuinfo,
0179     .get_irq        = mpic_get_irq,
0180     .time_init      = mpc86xx_time_init,
0181     .calibrate_decr     = generic_calibrate_decr,
0182     .progress       = udbg_progress,
0183 #ifdef CONFIG_PCI
0184     .pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
0185 #endif
0186 };