platforms/85xx/twr_p102x.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
0004  *
0005  * Author: Michael Johnston <michael.johnston@freescale.com>
0006  *
0007  * Description:
0008  * TWR-P102x Board Setup
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/errno.h>
0014 #include <linux/fsl/guts.h>
0015 #include <linux/pci.h>
0016 #include <linux/of_platform.h>
0017
0018 #include <asm/pci-bridge.h>
0019 #include <asm/udbg.h>
0020 #include <asm/mpic.h>
0021 #include <soc/fsl/qe/qe.h>
0022
0023 #include <sysdev/fsl_soc.h>
0024 #include <sysdev/fsl_pci.h>
0025 #include "smp.h"
0026
0027 #include "mpc85xx.h"
0028
0029 static void __init twr_p1025_pic_init(void)
0030 {
0031     struct mpic *mpic;
0032
0033     mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
0034             MPIC_SINGLE_DEST_CPU,
0035             0, 256, " OpenPIC  ");
0036
0037     BUG_ON(mpic == NULL);
0038     mpic_init(mpic);
0039 }
0040
0041 /* ************************************************************************
0042  *
0043  * Setup the architecture
0044  *
0045  */
0046 static void __init twr_p1025_setup_arch(void)
0047 {
0048     if (ppc_md.progress)
0049         ppc_md.progress("twr_p1025_setup_arch()", 0);
0050
0051     mpc85xx_smp_init();
0052
0053     fsl_pci_assign_primary();
0054
0055 #ifdef CONFIG_QUICC_ENGINE
0056     mpc85xx_qe_par_io_init();
0057
0058 #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
0059     if (machine_is(twr_p1025)) {
0060         struct ccsr_guts __iomem *guts;
0061         struct device_node *np;
0062
0063         np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
0064         if (np) {
0065             guts = of_iomap(np, 0);
0066             if (!guts)
0067                 pr_err("twr_p1025: could not map global utilities register\n");
0068             else {
0069             /* P1025 has pins muxed for QE and other functions. To
0070              * enable QE UEC mode, we need to set bit QE0 for UCC1
0071              * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
0072              * and QE12 for QE MII management signals in PMUXCR
0073              * register.
0074              * Set QE mux bits in PMUXCR */
0075             setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
0076                     MPC85xx_PMUXCR_QE(3) |
0077                     MPC85xx_PMUXCR_QE(9) |
0078                     MPC85xx_PMUXCR_QE(12));
0079             iounmap(guts);
0080
0081 #if IS_ENABLED(CONFIG_SERIAL_QE)
0082             /* On P1025TWR board, the UCC7 acted as UART port.
0083              * However, The UCC7's CTS pin is low level in default,
0084              * it will impact the transmission in full duplex
0085              * communication. So disable the Flow control pin PA18.
0086              * The UCC7 UART just can use RXD and TXD pins.
0087              */
0088             par_io_config_pin(0, 18, 0, 0, 0, 0);
0089 #endif
0090             /* Drive PB29 to CPLD low - CPLD will then change
0091              * muxing from LBC to QE */
0092             par_io_config_pin(1, 29, 1, 0, 0, 0);
0093             par_io_data_set(1, 29, 0);
0094             }
0095             of_node_put(np);
0096         }
0097     }
0098 #endif
0099 #endif  /* CONFIG_QUICC_ENGINE */
0100
0101     pr_info("TWR-P1025 board from Freescale Semiconductor\n");
0102 }
0103
0104 machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
0105
0106 static int __init twr_p1025_probe(void)
0107 {
0108     return of_machine_is_compatible("fsl,TWR-P1025");
0109 }
0110
0111 define_machine(twr_p1025) {
0112     .name           = "TWR-P1025",
0113     .probe          = twr_p1025_probe,
0114     .setup_arch     = twr_p1025_setup_arch,
0115     .init_IRQ       = twr_p1025_pic_init,
0116 #ifdef CONFIG_PCI
0117     .pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
0118 #endif
0119     .get_irq        = mpic_get_irq,
0120     .calibrate_decr     = generic_calibrate_decr,
0121     .progress       = udbg_progress,
0122 };