platforms/85xx/t1042rdb_diu.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * T1042 platform DIU operation
0004  *
0005  * Copyright 2014 Freescale Semiconductor Inc.
0006  */
0007
0008 #include <linux/init.h>
0009 #include <linux/io.h>
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014
0015 #include <sysdev/fsl_soc.h>
0016
0017 /*DIU Pixel ClockCR offset in scfg*/
0018 #define CCSR_SCFG_PIXCLKCR      0x28
0019
0020 /* DIU Pixel Clock bits of the PIXCLKCR */
0021 #define PIXCLKCR_PXCKEN     0x80000000
0022 #define PIXCLKCR_PXCKINV    0x40000000
0023 #define PIXCLKCR_PXCKDLY    0x0000FF00
0024 #define PIXCLKCR_PXCLK_MASK 0x00FF0000
0025
0026 /* Some CPLD register definitions */
0027 #define CPLD_DIUCSR     0x16
0028 #define CPLD_DIUCSR_DVIEN   0x80
0029 #define CPLD_DIUCSR_BACKLIGHT   0x0f
0030
0031 struct device_node *cpld_node;
0032
0033 /**
0034  * t1042rdb_set_monitor_port: switch the output to a different monitor port
0035  */
0036 static void t1042rdb_set_monitor_port(enum fsl_diu_monitor_port port)
0037 {
0038     void __iomem *cpld_base;
0039
0040     cpld_base = of_iomap(cpld_node, 0);
0041     if (!cpld_base) {
0042         pr_err("%s: Could not map cpld registers\n", __func__);
0043         goto exit;
0044     }
0045
0046     switch (port) {
0047     case FSL_DIU_PORT_DVI:
0048         /* Enable the DVI(HDMI) port, disable the DFP and
0049          * the backlight
0050          */
0051         clrbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_DVIEN);
0052         break;
0053     case FSL_DIU_PORT_LVDS:
0054         /*
0055          * LVDS also needs backlight enabled, otherwise the display
0056          * will be blank.
0057          */
0058         /* Enable the DFP port, disable the DVI*/
0059         setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 8);
0060         setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 4);
0061         setbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_BACKLIGHT);
0062         break;
0063     default:
0064         pr_err("%s: Unsupported monitor port %i\n", __func__, port);
0065     }
0066
0067     iounmap(cpld_base);
0068 exit:
0069     of_node_put(cpld_node);
0070 }
0071
0072 /**
0073  * t1042rdb_set_pixel_clock: program the DIU's clock
0074  * @pixclock: pixel clock in ps (pico seconds)
0075  */
0076 static void t1042rdb_set_pixel_clock(unsigned int pixclock)
0077 {
0078     struct device_node *scfg_np;
0079     void __iomem *scfg;
0080     unsigned long freq;
0081     u64 temp;
0082     u32 pxclk;
0083
0084     scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg");
0085     if (!scfg_np) {
0086         pr_err("%s: Missing scfg node. Can not display video.\n",
0087                __func__);
0088         return;
0089     }
0090
0091     scfg = of_iomap(scfg_np, 0);
0092     of_node_put(scfg_np);
0093     if (!scfg) {
0094         pr_err("%s: Could not map device. Can not display video.\n",
0095                __func__);
0096         return;
0097     }
0098
0099     /* Convert pixclock into frequency */
0100     temp = 1000000000000ULL;
0101     do_div(temp, pixclock);
0102     freq = temp;
0103
0104     /*
0105      * 'pxclk' is the ratio of the platform clock to the pixel clock.
0106      * This number is programmed into the PIXCLKCR register, and the valid
0107      * range of values is 2-255.
0108      */
0109     pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
0110     pxclk = clamp_t(u32, pxclk, 2, 255);
0111
0112     /* Disable the pixel clock, and set it to non-inverted and no delay */
0113     clrbits32(scfg + CCSR_SCFG_PIXCLKCR,
0114           PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK);
0115
0116     /* Enable the clock and set the pxclk */
0117     setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
0118
0119     iounmap(scfg);
0120 }
0121
0122 /**
0123  * t1042rdb_valid_monitor_port: set the monitor port for sysfs
0124  */
0125 static enum fsl_diu_monitor_port
0126 t1042rdb_valid_monitor_port(enum fsl_diu_monitor_port port)
0127 {
0128     switch (port) {
0129     case FSL_DIU_PORT_DVI:
0130     case FSL_DIU_PORT_LVDS:
0131         return port;
0132     default:
0133         return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
0134     }
0135 }
0136
0137 static int __init t1042rdb_diu_init(void)
0138 {
0139     cpld_node = of_find_compatible_node(NULL, NULL, "fsl,t1042rdb-cpld");
0140     if (!cpld_node)
0141         return 0;
0142
0143     diu_ops.set_monitor_port    = t1042rdb_set_monitor_port;
0144     diu_ops.set_pixel_clock     = t1042rdb_set_pixel_clock;
0145     diu_ops.valid_monitor_port  = t1042rdb_valid_monitor_port;
0146
0147     return 0;
0148 }
0149
0150 early_initcall(t1042rdb_diu_init);
0151
0152 MODULE_LICENSE("GPL");