platforms/85xx/smp.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Author: Andy Fleming <afleming@freescale.com>
0004  *     Kumar Gala <galak@kernel.crashing.org>
0005  *
0006  * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
0007  */
0008
0009 #include <linux/stddef.h>
0010 #include <linux/kernel.h>
0011 #include <linux/sched/hotplug.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/of.h>
0015 #include <linux/kexec.h>
0016 #include <linux/highmem.h>
0017 #include <linux/cpu.h>
0018 #include <linux/fsl/guts.h>
0019 #include <linux/pgtable.h>
0020
0021 #include <asm/machdep.h>
0022 #include <asm/page.h>
0023 #include <asm/mpic.h>
0024 #include <asm/cacheflush.h>
0025 #include <asm/dbell.h>
0026 #include <asm/code-patching.h>
0027 #include <asm/cputhreads.h>
0028 #include <asm/fsl_pm.h>
0029
0030 #include <sysdev/fsl_soc.h>
0031 #include <sysdev/mpic.h>
0032 #include "smp.h"
0033
0034 struct epapr_spin_table {
0035     u32 addr_h;
0036     u32 addr_l;
0037     u32 r3_h;
0038     u32 r3_l;
0039     u32 reserved;
0040     u32 pir;
0041 };
0042
0043 static u64 timebase;
0044 static int tb_req;
0045 static int tb_valid;
0046
0047 static void mpc85xx_give_timebase(void)
0048 {
0049     unsigned long flags;
0050
0051     local_irq_save(flags);
0052     hard_irq_disable();
0053
0054     while (!tb_req)
0055         barrier();
0056     tb_req = 0;
0057
0058     qoriq_pm_ops->freeze_time_base(true);
0059 #ifdef CONFIG_PPC64
0060     /*
0061      * e5500/e6500 have a workaround for erratum A-006958 in place
0062      * that will reread the timebase until TBL is non-zero.
0063      * That would be a bad thing when the timebase is frozen.
0064      *
0065      * Thus, we read it manually, and instead of checking that
0066      * TBL is non-zero, we ensure that TB does not change.  We don't
0067      * do that for the main mftb implementation, because it requires
0068      * a scratch register
0069      */
0070     {
0071         u64 prev;
0072
0073         asm volatile("mfspr %0, %1" : "=r" (timebase) :
0074                  "i" (SPRN_TBRL));
0075
0076         do {
0077             prev = timebase;
0078             asm volatile("mfspr %0, %1" : "=r" (timebase) :
0079                      "i" (SPRN_TBRL));
0080         } while (prev != timebase);
0081     }
0082 #else
0083     timebase = get_tb();
0084 #endif
0085     mb();
0086     tb_valid = 1;
0087
0088     while (tb_valid)
0089         barrier();
0090
0091     qoriq_pm_ops->freeze_time_base(false);
0092
0093     local_irq_restore(flags);
0094 }
0095
0096 static void mpc85xx_take_timebase(void)
0097 {
0098     unsigned long flags;
0099
0100     local_irq_save(flags);
0101     hard_irq_disable();
0102
0103     tb_req = 1;
0104     while (!tb_valid)
0105         barrier();
0106
0107     set_tb(timebase >> 32, timebase & 0xffffffff);
0108     isync();
0109     tb_valid = 0;
0110
0111     local_irq_restore(flags);
0112 }
0113
0114 #ifdef CONFIG_HOTPLUG_CPU
0115 static void smp_85xx_cpu_offline_self(void)
0116 {
0117     unsigned int cpu = smp_processor_id();
0118
0119     local_irq_disable();
0120     hard_irq_disable();
0121     /* mask all irqs to prevent cpu wakeup */
0122     qoriq_pm_ops->irq_mask(cpu);
0123
0124     idle_task_exit();
0125
0126     mtspr(SPRN_TCR, 0);
0127     mtspr(SPRN_TSR, mfspr(SPRN_TSR));
0128
0129     generic_set_cpu_dead(cpu);
0130
0131     cur_cpu_spec->cpu_down_flush();
0132
0133     qoriq_pm_ops->cpu_die(cpu);
0134
0135     while (1)
0136         ;
0137 }
0138
0139 static void qoriq_cpu_kill(unsigned int cpu)
0140 {
0141     int i;
0142
0143     for (i = 0; i < 500; i++) {
0144         if (is_cpu_dead(cpu)) {
0145 #ifdef CONFIG_PPC64
0146             paca_ptrs[cpu]->cpu_start = 0;
0147 #endif
0148             return;
0149         }
0150         msleep(20);
0151     }
0152     pr_err("CPU%d didn't die...\n", cpu);
0153 }
0154 #endif
0155
0156 /*
0157  * To keep it compatible with old boot program which uses
0158  * cache-inhibit spin table, we need to flush the cache
0159  * before accessing spin table to invalidate any staled data.
0160  * We also need to flush the cache after writing to spin
0161  * table to push data out.
0162  */
0163 static inline void flush_spin_table(void *spin_table)
0164 {
0165     flush_dcache_range((ulong)spin_table,
0166         (ulong)spin_table + sizeof(struct epapr_spin_table));
0167 }
0168
0169 static inline u32 read_spin_table_addr_l(void *spin_table)
0170 {
0171     flush_dcache_range((ulong)spin_table,
0172         (ulong)spin_table + sizeof(struct epapr_spin_table));
0173     return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
0174 }
0175
0176 #ifdef CONFIG_PPC64
0177 static void wake_hw_thread(void *info)
0178 {
0179     void fsl_secondary_thread_init(void);
0180     unsigned long inia;
0181     int cpu = *(const int *)info;
0182
0183     inia = *(unsigned long *)fsl_secondary_thread_init;
0184     book3e_start_thread(cpu_thread_in_core(cpu), inia);
0185 }
0186 #endif
0187
0188 static int smp_85xx_start_cpu(int cpu)
0189 {
0190     int ret = 0;
0191     struct device_node *np;
0192     const u64 *cpu_rel_addr;
0193     unsigned long flags;
0194     int ioremappable;
0195     int hw_cpu = get_hard_smp_processor_id(cpu);
0196     struct epapr_spin_table __iomem *spin_table;
0197
0198     np = of_get_cpu_node(cpu, NULL);
0199     cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
0200     if (!cpu_rel_addr) {
0201         pr_err("No cpu-release-addr for cpu %d\n", cpu);
0202         return -ENOENT;
0203     }
0204
0205     /*
0206      * A secondary core could be in a spinloop in the bootpage
0207      * (0xfffff000), somewhere in highmem, or somewhere in lowmem.
0208      * The bootpage and highmem can be accessed via ioremap(), but
0209      * we need to directly access the spinloop if its in lowmem.
0210      */
0211     ioremappable = *cpu_rel_addr > virt_to_phys(high_memory - 1);
0212
0213     /* Map the spin table */
0214     if (ioremappable)
0215         spin_table = ioremap_coherent(*cpu_rel_addr,
0216                           sizeof(struct epapr_spin_table));
0217     else
0218         spin_table = phys_to_virt(*cpu_rel_addr);
0219
0220     local_irq_save(flags);
0221     hard_irq_disable();
0222
0223     if (qoriq_pm_ops && qoriq_pm_ops->cpu_up_prepare)
0224         qoriq_pm_ops->cpu_up_prepare(cpu);
0225
0226     /* if cpu is not spinning, reset it */
0227     if (read_spin_table_addr_l(spin_table) != 1) {
0228         /*
0229          * We don't set the BPTR register here since it already points
0230          * to the boot page properly.
0231          */
0232         mpic_reset_core(cpu);
0233
0234         /*
0235          * wait until core is ready...
0236          * We need to invalidate the stale data, in case the boot
0237          * loader uses a cache-inhibited spin table.
0238          */
0239         if (!spin_event_timeout(
0240                 read_spin_table_addr_l(spin_table) == 1,
0241                 10000, 100)) {
0242             pr_err("timeout waiting for cpu %d to reset\n",
0243                 hw_cpu);
0244             ret = -EAGAIN;
0245             goto err;
0246         }
0247     }
0248
0249     flush_spin_table(spin_table);
0250     out_be32(&spin_table->pir, hw_cpu);
0251 #ifdef CONFIG_PPC64
0252     out_be64((u64 *)(&spin_table->addr_h),
0253         __pa(ppc_function_entry(generic_secondary_smp_init)));
0254 #else
0255 #ifdef CONFIG_PHYS_ADDR_T_64BIT
0256     /*
0257      * We need also to write addr_h to spin table for systems
0258      * in which their physical memory start address was configured
0259      * to above 4G, otherwise the secondary core can not get
0260      * correct entry to start from.
0261      */
0262     out_be32(&spin_table->addr_h, __pa(__early_start) >> 32);
0263 #endif
0264     out_be32(&spin_table->addr_l, __pa(__early_start));
0265 #endif
0266     flush_spin_table(spin_table);
0267 err:
0268     local_irq_restore(flags);
0269
0270     if (ioremappable)
0271         iounmap(spin_table);
0272
0273     return ret;
0274 }
0275
0276 static int smp_85xx_kick_cpu(int nr)
0277 {
0278     int ret = 0;
0279 #ifdef CONFIG_PPC64
0280     int primary = nr;
0281 #endif
0282
0283     WARN_ON(nr < 0 || nr >= num_possible_cpus());
0284
0285     pr_debug("kick CPU #%d\n", nr);
0286
0287 #ifdef CONFIG_PPC64
0288     if (threads_per_core == 2) {
0289         if (WARN_ON_ONCE(!cpu_has_feature(CPU_FTR_SMT)))
0290             return -ENOENT;
0291
0292         booting_thread_hwid = cpu_thread_in_core(nr);
0293         primary = cpu_first_thread_sibling(nr);
0294
0295         if (qoriq_pm_ops && qoriq_pm_ops->cpu_up_prepare)
0296             qoriq_pm_ops->cpu_up_prepare(nr);
0297
0298         /*
0299          * If either thread in the core is online, use it to start
0300          * the other.
0301          */
0302         if (cpu_online(primary)) {
0303             smp_call_function_single(primary,
0304                     wake_hw_thread, &nr, 1);
0305             goto done;
0306         } else if (cpu_online(primary + 1)) {
0307             smp_call_function_single(primary + 1,
0308                     wake_hw_thread, &nr, 1);
0309             goto done;
0310         }
0311
0312         /*
0313          * If getting here, it means both threads in the core are
0314          * offline. So start the primary thread, then it will start
0315          * the thread specified in booting_thread_hwid, the one
0316          * corresponding to nr.
0317          */
0318
0319     } else if (threads_per_core == 1) {
0320         /*
0321          * If one core has only one thread, set booting_thread_hwid to
0322          * an invalid value.
0323          */
0324         booting_thread_hwid = INVALID_THREAD_HWID;
0325
0326     } else if (threads_per_core > 2) {
0327         pr_err("Do not support more than 2 threads per CPU.");
0328         return -EINVAL;
0329     }
0330
0331     ret = smp_85xx_start_cpu(primary);
0332     if (ret)
0333         return ret;
0334
0335 done:
0336     paca_ptrs[nr]->cpu_start = 1;
0337     generic_set_cpu_up(nr);
0338
0339     return ret;
0340 #else
0341     ret = smp_85xx_start_cpu(nr);
0342     if (ret)
0343         return ret;
0344
0345     generic_set_cpu_up(nr);
0346
0347     return ret;
0348 #endif
0349 }
0350
0351 struct smp_ops_t smp_85xx_ops = {
0352     .cause_nmi_ipi = NULL,
0353     .kick_cpu = smp_85xx_kick_cpu,
0354     .cpu_bootable = smp_generic_cpu_bootable,
0355 #ifdef CONFIG_HOTPLUG_CPU
0356     .cpu_disable    = generic_cpu_disable,
0357     .cpu_die    = generic_cpu_die,
0358 #endif
0359 #if defined(CONFIG_KEXEC_CORE) && !defined(CONFIG_PPC64)
0360     .give_timebase  = smp_generic_give_timebase,
0361     .take_timebase  = smp_generic_take_timebase,
0362 #endif
0363 };
0364
0365 #ifdef CONFIG_KEXEC_CORE
0366 #ifdef CONFIG_PPC32
0367 atomic_t kexec_down_cpus = ATOMIC_INIT(0);
0368
0369 static void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
0370 {
0371     local_irq_disable();
0372
0373     if (secondary) {
0374         cur_cpu_spec->cpu_down_flush();
0375         atomic_inc(&kexec_down_cpus);
0376         /* loop forever */
0377         while (1);
0378     }
0379 }
0380
0381 static void mpc85xx_smp_kexec_down(void *arg)
0382 {
0383     if (ppc_md.kexec_cpu_down)
0384         ppc_md.kexec_cpu_down(0,1);
0385 }
0386 #else
0387 static void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
0388 {
0389     int cpu = smp_processor_id();
0390     int sibling = cpu_last_thread_sibling(cpu);
0391     bool notified = false;
0392     int disable_cpu;
0393     int disable_threadbit = 0;
0394     long start = mftb();
0395     long now;
0396
0397     local_irq_disable();
0398     hard_irq_disable();
0399     mpic_teardown_this_cpu(secondary);
0400
0401     if (cpu == crashing_cpu && cpu_thread_in_core(cpu) != 0) {
0402         /*
0403          * We enter the crash kernel on whatever cpu crashed,
0404          * even if it's a secondary thread.  If that's the case,
0405          * disable the corresponding primary thread.
0406          */
0407         disable_threadbit = 1;
0408         disable_cpu = cpu_first_thread_sibling(cpu);
0409     } else if (sibling != crashing_cpu &&
0410            cpu_thread_in_core(cpu) == 0 &&
0411            cpu_thread_in_core(sibling) != 0) {
0412         disable_threadbit = 2;
0413         disable_cpu = sibling;
0414     }
0415
0416     if (disable_threadbit) {
0417         while (paca_ptrs[disable_cpu]->kexec_state < KEXEC_STATE_REAL_MODE) {
0418             barrier();
0419             now = mftb();
0420             if (!notified && now - start > 1000000) {
0421                 pr_info("%s/%d: waiting for cpu %d to enter KEXEC_STATE_REAL_MODE (%d)\n",
0422                     __func__, smp_processor_id(),
0423                     disable_cpu,
0424                     paca_ptrs[disable_cpu]->kexec_state);
0425                 notified = true;
0426             }
0427         }
0428
0429         if (notified) {
0430             pr_info("%s: cpu %d done waiting\n",
0431                 __func__, disable_cpu);
0432         }
0433
0434         mtspr(SPRN_TENC, disable_threadbit);
0435         while (mfspr(SPRN_TENSR) & disable_threadbit)
0436             cpu_relax();
0437     }
0438 }
0439 #endif
0440
0441 static void mpc85xx_smp_machine_kexec(struct kimage *image)
0442 {
0443 #ifdef CONFIG_PPC32
0444     int timeout = INT_MAX;
0445     int i, num_cpus = num_present_cpus();
0446
0447     if (image->type == KEXEC_TYPE_DEFAULT)
0448         smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
0449
0450     while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
0451         ( timeout > 0 ) )
0452     {
0453         timeout--;
0454     }
0455
0456     if ( !timeout )
0457         printk(KERN_ERR "Unable to bring down secondary cpu(s)");
0458
0459     for_each_online_cpu(i)
0460     {
0461         if ( i == smp_processor_id() ) continue;
0462         mpic_reset_core(i);
0463     }
0464 #endif
0465
0466     default_machine_kexec(image);
0467 }
0468 #endif /* CONFIG_KEXEC_CORE */
0469
0470 static void smp_85xx_setup_cpu(int cpu_nr)
0471 {
0472     mpic_setup_this_cpu();
0473 }
0474
0475 void __init mpc85xx_smp_init(void)
0476 {
0477     struct device_node *np;
0478
0479
0480     np = of_find_node_by_type(NULL, "open-pic");
0481     if (np) {
0482         smp_85xx_ops.probe = smp_mpic_probe;
0483         smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
0484         smp_85xx_ops.message_pass = smp_mpic_message_pass;
0485     } else
0486         smp_85xx_ops.setup_cpu = NULL;
0487
0488     if (cpu_has_feature(CPU_FTR_DBELL)) {
0489         /*
0490          * If left NULL, .message_pass defaults to
0491          * smp_muxed_ipi_message_pass
0492          */
0493         smp_85xx_ops.message_pass = NULL;
0494         smp_85xx_ops.cause_ipi = doorbell_global_ipi;
0495         smp_85xx_ops.probe = NULL;
0496     }
0497
0498 #ifdef CONFIG_FSL_CORENET_RCPM
0499     /* Assign a value to qoriq_pm_ops on PPC_E500MC */
0500     fsl_rcpm_init();
0501 #else
0502     /* Assign a value to qoriq_pm_ops on !PPC_E500MC */
0503     mpc85xx_setup_pmc();
0504 #endif
0505     if (qoriq_pm_ops) {
0506         smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
0507         smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
0508 #ifdef CONFIG_HOTPLUG_CPU
0509         smp_85xx_ops.cpu_offline_self = smp_85xx_cpu_offline_self;
0510         smp_85xx_ops.cpu_die = qoriq_cpu_kill;
0511 #endif
0512     }
0513     smp_ops = &smp_85xx_ops;
0514
0515 #ifdef CONFIG_KEXEC_CORE
0516     ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
0517     ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;
0518 #endif
0519 }