platforms/85xx/mpc85xx_ds.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * MPC85xx DS Board Setup
0004  *
0005  * Author Xianghua Xiao (x.xiao@freescale.com)
0006  * Roy Zang <tie-fei.zang@freescale.com>
0007  *  - Add PCI/PCI Exprees support
0008  * Copyright 2007 Freescale Semiconductor Inc.
0009  */
0010
0011 #include <linux/stddef.h>
0012 #include <linux/kernel.h>
0013 #include <linux/pci.h>
0014 #include <linux/kdev_t.h>
0015 #include <linux/delay.h>
0016 #include <linux/seq_file.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_platform.h>
0020
0021 #include <asm/time.h>
0022 #include <asm/machdep.h>
0023 #include <asm/pci-bridge.h>
0024 #include <mm/mmu_decl.h>
0025 #include <asm/udbg.h>
0026 #include <asm/mpic.h>
0027 #include <asm/i8259.h>
0028 #include <asm/swiotlb.h>
0029
0030 #include <sysdev/fsl_soc.h>
0031 #include <sysdev/fsl_pci.h>
0032 #include "smp.h"
0033
0034 #include "mpc85xx.h"
0035
0036 #undef DEBUG
0037
0038 #ifdef DEBUG
0039 #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
0040 #else
0041 #define DBG(fmt, args...)
0042 #endif
0043
0044 #ifdef CONFIG_PPC_I8259
0045 static void mpc85xx_8259_cascade(struct irq_desc *desc)
0046 {
0047     struct irq_chip *chip = irq_desc_get_chip(desc);
0048     unsigned int cascade_irq = i8259_irq();
0049
0050     if (cascade_irq) {
0051         generic_handle_irq(cascade_irq);
0052     }
0053     chip->irq_eoi(&desc->irq_data);
0054 }
0055 #endif  /* CONFIG_PPC_I8259 */
0056
0057 void __init mpc85xx_ds_pic_init(void)
0058 {
0059     struct mpic *mpic;
0060 #ifdef CONFIG_PPC_I8259
0061     struct device_node *np;
0062     struct device_node *cascade_node = NULL;
0063     int cascade_irq;
0064 #endif
0065     if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) {
0066         mpic = mpic_alloc(NULL, 0,
0067             MPIC_NO_RESET |
0068             MPIC_BIG_ENDIAN |
0069             MPIC_SINGLE_DEST_CPU,
0070             0, 256, " OpenPIC  ");
0071     } else {
0072         mpic = mpic_alloc(NULL, 0,
0073               MPIC_BIG_ENDIAN |
0074               MPIC_SINGLE_DEST_CPU,
0075             0, 256, " OpenPIC  ");
0076     }
0077
0078     BUG_ON(mpic == NULL);
0079     mpic_init(mpic);
0080
0081 #ifdef CONFIG_PPC_I8259
0082     /* Initialize the i8259 controller */
0083     for_each_node_by_type(np, "interrupt-controller")
0084         if (of_device_is_compatible(np, "chrp,iic")) {
0085         cascade_node = np;
0086         break;
0087     }
0088
0089     if (cascade_node == NULL) {
0090         printk(KERN_DEBUG "Could not find i8259 PIC\n");
0091         return;
0092     }
0093
0094     cascade_irq = irq_of_parse_and_map(cascade_node, 0);
0095     if (!cascade_irq) {
0096         printk(KERN_ERR "Failed to map cascade interrupt\n");
0097         return;
0098     }
0099
0100     DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq);
0101
0102     i8259_init(cascade_node, 0);
0103     of_node_put(cascade_node);
0104
0105     irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
0106 #endif  /* CONFIG_PPC_I8259 */
0107 }
0108
0109 #ifdef CONFIG_PCI
0110 extern int uli_exclude_device(struct pci_controller *hose,
0111                 u_char bus, u_char devfn);
0112
0113 static struct device_node *pci_with_uli;
0114
0115 static int mpc85xx_exclude_device(struct pci_controller *hose,
0116                    u_char bus, u_char devfn)
0117 {
0118     if (hose->dn == pci_with_uli)
0119         return uli_exclude_device(hose, bus, devfn);
0120
0121     return PCIBIOS_SUCCESSFUL;
0122 }
0123 #endif  /* CONFIG_PCI */
0124
0125 static void __init mpc85xx_ds_uli_init(void)
0126 {
0127 #ifdef CONFIG_PCI
0128     struct device_node *node;
0129
0130     /* See if we have a ULI under the primary */
0131
0132     node = of_find_node_by_name(NULL, "uli1575");
0133     while ((pci_with_uli = of_get_parent(node))) {
0134         of_node_put(node);
0135         node = pci_with_uli;
0136
0137         if (pci_with_uli == fsl_pci_primary) {
0138             ppc_md.pci_exclude_device = mpc85xx_exclude_device;
0139             break;
0140         }
0141     }
0142 #endif
0143 }
0144
0145 /*
0146  * Setup the architecture
0147  */
0148 static void __init mpc85xx_ds_setup_arch(void)
0149 {
0150     if (ppc_md.progress)
0151         ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
0152
0153     swiotlb_detect_4g();
0154     fsl_pci_assign_primary();
0155     mpc85xx_ds_uli_init();
0156     mpc85xx_smp_init();
0157
0158     printk("MPC85xx DS board from Freescale Semiconductor\n");
0159 }
0160
0161 /*
0162  * Called very early, device-tree isn't unflattened
0163  */
0164 static int __init mpc8544_ds_probe(void)
0165 {
0166     return !!of_machine_is_compatible("MPC8544DS");
0167 }
0168
0169 machine_arch_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
0170 machine_arch_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
0171 machine_arch_initcall(p2020_ds, mpc85xx_common_publish_devices);
0172
0173 /*
0174  * Called very early, device-tree isn't unflattened
0175  */
0176 static int __init mpc8572_ds_probe(void)
0177 {
0178     return !!of_machine_is_compatible("fsl,MPC8572DS");
0179 }
0180
0181 /*
0182  * Called very early, device-tree isn't unflattened
0183  */
0184 static int __init p2020_ds_probe(void)
0185 {
0186     return !!of_machine_is_compatible("fsl,P2020DS");
0187 }
0188
0189 define_machine(mpc8544_ds) {
0190     .name           = "MPC8544 DS",
0191     .probe          = mpc8544_ds_probe,
0192     .setup_arch     = mpc85xx_ds_setup_arch,
0193     .init_IRQ       = mpc85xx_ds_pic_init,
0194 #ifdef CONFIG_PCI
0195     .pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
0196     .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
0197 #endif
0198     .get_irq        = mpic_get_irq,
0199     .calibrate_decr     = generic_calibrate_decr,
0200     .progress       = udbg_progress,
0201 };
0202
0203 define_machine(mpc8572_ds) {
0204     .name           = "MPC8572 DS",
0205     .probe          = mpc8572_ds_probe,
0206     .setup_arch     = mpc85xx_ds_setup_arch,
0207     .init_IRQ       = mpc85xx_ds_pic_init,
0208 #ifdef CONFIG_PCI
0209     .pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
0210     .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
0211 #endif
0212     .get_irq        = mpic_get_irq,
0213     .calibrate_decr     = generic_calibrate_decr,
0214     .progress       = udbg_progress,
0215 };
0216
0217 define_machine(p2020_ds) {
0218     .name           = "P2020 DS",
0219     .probe          = p2020_ds_probe,
0220     .setup_arch     = mpc85xx_ds_setup_arch,
0221     .init_IRQ       = mpc85xx_ds_pic_init,
0222 #ifdef CONFIG_PCI
0223     .pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
0224     .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
0225 #endif
0226     .get_irq        = mpic_get_irq,
0227     .calibrate_decr     = generic_calibrate_decr,
0228     .progress       = udbg_progress,
0229 };